Phil C. Knag

Orcid: 0000-0001-6794-8806

According to our database1, Phil C. Knag authored at least 15 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm.
IEEE J. Solid State Circuits, March, 2024

2023
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS.
IEEE J. Solid State Circuits, 2023

microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2021

2020
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2019

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018


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