Mahboobe Sadeghipourrudsari

Orcid: 0009-0002-1945-155X

According to our database1, Mahboobe Sadeghipourrudsari authored at least 16 papers between 2020 and 2026.

Collaborative distances:

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Concurrent Fault Detection for Binary Neural Network Accelerators via On-Chip Voltage Monitoring.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

MF-ECC: Memory-Free Error Correction for Hyperdimensional Computing Edge Accelerators.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
CED-HDC: Lightweight Concurrent Error Detection for Reliable Hyperdimensional Computing.
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

Collide & Conquer: Side-channel Attack on Hyper-dimensional Computing (HDC) Accelerators.
Proceedings of the IEEE International Test Conference in Asia, 2025

Lightweight Concurrent Out-of-Distribution Detection in Hyperdimensional Computing Hardware.
Proceedings of the 31st IEEE International Symposium on On-Line Testing and Robust System Design, 2025

Non-Uniform Error Correction for Hyperdimensional Computing Edge Accelerators.
Proceedings of the IEEE European Test Symposium, 2025


Towards Functional Safety of Neural Network Hardware Accelerators: Concurrent Out-of-Distribution Detection in Hardware Using Power Side-Channel Analysis.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
E<sup>3</sup>HDC: Energy Efficient Encoding for Hyper-Dimensional Computing on Edge Devices.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

OTFGEncoder - HDC: Hardware-efficient Encoding Techniques for Hyperdimensional Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
LiFi-CFI: Light-weight Fine-grained Hardware CFI Protection for RISC-V.
Proceedings of the 2023 IEEE International Conference on Design, 2023

2022
A Secure Canary-Based Hardware Approach Against ROP.
Proceedings of the Italian Conference on Cybersecurity (ITASEC 2022), 2022

Concurrent Error Detection for LSTM Accelerators.
Proceedings of the IEEE European Test Symposium, 2022

2021
n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

AFTAB: A RISC-V Implementation with Configurable Gateways for Security.
Proceedings of the IEEE East-West Design & Test Symposium, 2021

2020
DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020


  Loading...