Charles E. Stroud

According to our database1, Charles E. Stroud authored at least 61 papers between 1988 and 2011.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2005, "For contributions to built-in self-test of integrated circuits.".

Timeline

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On csauthors.net:

Bibliography

2011
Selective Spectrum Analysis for Analog Measurements.
IEEE Trans. Industrial Electronics, 2011

2010
On-Line Single Event Upset Detection and Correction in Field Programmable Gate Array Configuration Memories.
I. J. Comput. Appl., 2010

The First Clock Cycle Is A Real BIST.
Proceedings of the 2010 International Conference on Embedded Systems & Applications, 2010

2009
On Built-In Self-Test for Adders.
J. Electronic Testing, 2009

Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Soft Core Embedded Processor Based Built-In Self-Test of FPGAs.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Application of Embedded Systems in Low Earth Orbit for Measurement of Ionospheric Anomalies.
Proceedings of the 2009 International Conference on Embedded Systems & Applications, 2009

Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs.
Proceedings of the 2009 International Conference on Embedded Systems & Applications, 2009

Embedded Processor Based Fault Injection and SEU Emulation for FPGAs.
Proceedings of the 2009 International Conference on Embedded Systems & Applications, 2009

Built-in Self-Test for Memory Resources in Virtex-4 Field Programmable Gate Arrays.
Proceedings of the ISCA 24th International Conference on Computers and Their Applications, 2009

Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs.
Proceedings of the ISCA 24th International Conference on Computers and Their Applications, 2009

2008
Logic Testing.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

2007
Online Fault Tolerance for FPGA Logic Blocks.
IEEE Trans. VLSI Syst., 2007

FPGA-Based Analog Functional Measurements for Adaptive Control in Mixed-Signal Systems.
IEEE Trans. Industrial Electronics, 2007

Noise Figure Measurement Using Mixed-Signal BIST.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Automatic linearity and frequency response tests with built-in pattern generator and analyzer.
IEEE Trans. VLSI Syst., 2006

An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults.
J. Electronic Testing, 2006

Analog frequency response measurement in mixed-signal systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

An Architecture for Fail-Silent Operation of FPGAs and Configurable SoCs.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

2005
Built-in self-test for automatic analog frequency response measurement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Built-In Self-Test and Diagnosis of Multiple Embedded Cores in SoCs.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in System-on-Chip Devices.
Proceedings of the 20th International Conference on Computers and Their Applications, 2005

2004
Online BIST and BIST-based diagnosis of FPGA logic blocks.
IEEE Trans. VLSI Syst., 2004

Built-In Self-Test for System-on-Chip: A Case Study.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
BIST-Based Delay-Fault Testing in FPGAs.
J. Electronic Testing, 2003

BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
BIST-Based Diagnosis of FPGA Interconnect.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

BIST-Based Delay-Fault Testing in FPGAs.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Using embedded FPGAs for SoC yield improvement.
Proceedings of the 39th Design Automation Conference, 2002

2001
BIST-based test and diagnosis of FPGA logic blocks.
IEEE Trans. VLSI Syst., 2001

Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them?
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems.
Proceedings of the 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 2001

On-Line Fault Tolerance for FPGA Interconnect with Roving STARs.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
A New Method for Testing Re-Programmable PLAs.
J. Electronic Testing, 2000

Bridging fault extraction from physical design data for manufacturing test development.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

DIST-based detection and diagnosis of multiple faults in FPGAs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Improving On-Line BIST-Based Diagnosis for Roving STARs.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

Performance Penalty for Fault Tolerance in Roving STARs.
Proceedings of the Field-Programmable Logic and Applications, 2000

Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Built-in self-test of FPGA interconnect.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
BIST-Based Diagnostics of FPGA Logic Blocks.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

A Parameterized VHDL Library for On-Line Testing.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!).
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Using ILA Testing for BIST in FPGAs.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

1995
Multiple error detection and identification via signature analysis.
J. Electronic Testing, 1995

Improving the efficiency of error identification via signature analysis.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A built-in self test scheme for VLSI.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Reliability of majority voting based VLSI fault-tolerant circuits.
IEEE Trans. VLSI Syst., 1994

1993
Testability and test generation for majority voting fault-tolerant circuits.
J. Electronic Testing, 1993

1991
Distractions in Design for Testability and Built-Is Self-Test.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Built-In Self-Test for High-Speed Data-Path Circuitry.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
Parallel Processing and Hardware Acceleration for Synthesis of VLSI Devices from Behavioral Models.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989
Design for Testability and Test Generation for Static Redundancy System Level Fault-Tolerant Circuits.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
An Automated BIST Approach for General Sequential Logic Synthesis.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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