Charvaka Duvvury

According to our database, Charvaka Duvvury authored at least 14 papers between 1993 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

System efficient ESD design.

Harald Gossner, Charvaka Duvvury

Microelectron. Reliab., 2015

2006

Gate oxide failures due to anomalous stress from HBM ESD testers.

Charvaka Duvvury, Robert Steinhoff, Gianluca Boselli, Vijay Reddy, Hans Kunz, Steve Marum, Roger Cline

Microelectron. Reliab., 2006

Circuit design issues in multi-gate FET CMOS technologies.

Christian Pacha, Klaus von Arnim, Thomas Schulz, Weize Xiong, Michael Gostkowski, Gerhard Knoblinger, Andrew Marshall, Thomas Nirschl, Jörg Berthold, Christian Russ, Harald Gossner, Charvaka Duvvury, Paul Patruno, C. Rinn Cleavelin, Klaus Schruefer

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies.

Gianluca Boselli, Charvaka Duvvury

Microelectron. Reliab., 2005

2004

Latchup in voltage tolerant circuits: a new phenomenon.

Jorge Salcedo-Suñer, Charvaka Duvvury, Roger Cline, Alfonso Cadena-Hernandez

Microelectron. Reliab., 2004

2002

Development of substrate-pumped nMOS protection for a 0.13 mum technology.

Craig Salling, Jerry Hu, Jeff Wu, Charvaka Duvvury, Roger Cline, Rith Pok

Microelectron. Reliab., 2002

Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract).

Charvaka Duvvury

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001

A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies.

Steven H. Voldman, W. Anderson, R. Ashton, M. Chaine, Charvaka Duvvury, T. Maloney, E. Worley

Microelectron. Reliab., 2001

Issues in Deep Submicron State-of-the-Art ESD Design.

Charvaka Duvvury

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

ESD protection device issues for IC designs.

Charvaka Duvvury

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

ESD: Design For IC Chip Quality and Reliability.

Charvaka Duvvury

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1994

Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices.

Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993

ESD: a pervasive reliability concern for IC technologies.

Charvaka Duvvury, Ajith Amerasekera

Proc. IEEE, 1993

Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices.

Carlos H. Díaz, Charvaka Duvvury, Sung-Mo Kang

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993