Vijay Reddy

According to our database1, Vijay Reddy authored at least 19 papers between 2004 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2022
A Critical Examination of the TCAD Modeling of Hot Carrier Degradation for LDMOS Transistors.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
Quantifying Region-Specific Hot Carrier Degradation in LDMOS Transistors Using a Novel Charge Pumping Technique.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020
A Novel 'I-V Spectroscopy' Technique to Deconvolve Threshold Voltage and Mobility Degradation in LDMOS Transistors.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Investigating the Aging Dynamics of Diode-Connected MOS Devices Using an Array-Based Characterization Vehicle in a 65nm Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2016
Controlling Aging in Timing-Critical Paths.
IEEE Des. Test, 2016

2014
Recovery modeling of negative bias temperature instability (NBTI) for SPICE-compatible circuit aging simulators.
ACM J. Emerg. Technol. Comput. Syst., 2014

Reliability improvement of logic and clock paths in power-efficient designs.
ACM J. Emerg. Technol. Comput. Syst., 2014

Asymmetric aging of clock networks in power efficient designs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
A design-for-reliability approach based on grading library cells for aging effects.
Proceedings of the 2013 IEEE International Test Conference, 2013

Performance entitlement by exploiting transistor's BTI recovery.
Proceedings of the International Symposium on Quality Electronic Design, 2013

ACE: A robust variability and aging sensor for high-k/metal gate SoC.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors.
IEEE Des. Test Comput., 2012

2009
Circuit aging prediction for low-power operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Statistical prediction of circuit aging under process variations.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Gate oxide failures due to anomalous stress from HBM ESD testers.
Microelectron. Reliab., 2006

2005
Impact of negative bias temperature instability on digital circuit reliability.
Microelectron. Reliab., 2005

2004
Impact of Negative Bias Temperature Instability on Product Parametric Drift.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004


  Loading...