Ajith Amerasekera

According to our database1, Ajith Amerasekera authored at least 12 papers between 2002 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2012, "For leadership in semiconductor innovation and contributions to circuit design".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems.
IEEE J. Solid State Circuits, 2014

ES2: Data centers to support tomorrow's cloud.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

ES3: High-speed communications on 4 wheels: What's in your next car?
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Foreword.
Proceedings of the Symposium on VLSI Circuits, 2012

2010
Ultra low power electronics in the next decade.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2008
The Changing Design Landscape.
IEEE Des. Test Comput., 2008

2007
Concurrent Optimization of Technology and Design for Nano CMOS.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2002
A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002


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