Churoo Park

According to our database¹, Churoo Park authored at least 4 papers between 1994 and 2011.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2011

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2011

2010

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2006

A 512-mb DDR3 SDRAM prototype with C<sub>IO</sub> minimization and self-calibration techniques.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

1994

16-Mb synchronous DRAM with 125-Mbyte/s data rate.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, April, 1994

Churoo Park

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