Hoeju Chung
According to our database1,
Hoeju Chung
authored at least 12 papers
between 2006 and 2021.
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Bibliography
2021
2020
Improving Memory Reliability by Bounding DRAM Faults: DDR5 improved reliability features.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020
2015
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.
IEEE J. Solid State Circuits, 2015
2014
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
2009
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits, 2007
2006
A 512-mb DDR3 SDRAM prototype with C<sub>IO</sub> minimization and self-calibration techniques.
IEEE J. Solid State Circuits, 2006
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006