Daehoon Kim

Orcid: 0000-0003-0837-0877

Affiliations:
  • Yonsei University, Department of System Semiconductor Engineering, Seoul, South Korea
  • Daegu Gyeongbuk Institute of Science and Technology (DGIST), Department of Information and Communication Engineering, Daegu, South Korea
  • Korea Advanced Institute of of Science and Technology (KAIST), Daejeon, South Korea (PhD 2014)


According to our database1, Daehoon Kim authored at least 36 papers between 2010 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Jack Unit: An Area- and Energy-Efficient Multiply-Accumulate (MAC) Unit Supporting Diverse Data Formats.
CoRR, July, 2025

pNet-gem5: Full-System Simulation With High-Performance Networking Enabled by Parallel Network Packet Processing.
IEEE Comput. Archit. Lett., 2025

SAFE: Sharing-Aware Prefetching for Efficient GPU Memory Management With Unified Virtual Memory.
IEEE Comput. Archit. Lett., 2025

CABANA : Cluster-Aware Query Batching for Accelerating Billion-Scale ANNS With Intel AMX.
IEEE Comput. Archit. Lett., 2025

Cooperative Memory Deduplication With Intel Data Streaming Accelerator.
IEEE Comput. Archit. Lett., 2025

RoPIM: A Processing-in-Memory Architecture for Accelerating Rotary Positional Embedding in Transformer Models.
IEEE Comput. Archit. Lett., 2025

Para-ksm: Parallelized Memory Deduplication with Data Streaming Accelerator.
Proceedings of the 2025 USENIX Annual Technical Conference, 2025

BrokenSleep: Remote Power Timing Attack Exploiting Processor Idle States.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

Co-UP: Comprehensive Core and Uncore Power Management for Latency-Critical Workloads.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
vSPACE: Supporting Parallel Network Packet Processing in Virtualized Environments through Dynamic Core Management.
Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024

2023
CoreNap: Energy Efficient Core Allocation for Latency-Critical Workloads.
IEEE Comput. Archit. Lett., 2023

T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving.
IEEE Comput. Archit. Lett., 2023

NoHammer: Preventing Row Hammer With Last-Level Cache Management.
IEEE Comput. Archit. Lett., 2023

2022
IDIO: Network-Driven, Inbound Network Data Orchestration on Server Processors.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021
Deep Partitioned Training From Near-Storage Computing to DNN Accelerators.
IEEE Comput. Archit. Lett., 2021

IDIO: Orchestrating Inbound Network Data on Server Processors.
IEEE Comput. Archit. Lett., 2021

GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

NMAP: Power Management Based on Network Packet Processing Mode Transition for Latency-Critical Workloads.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

InnerSP: A Memory Efficient Sparse Matrix Multiplication Accelerator with Locality-Aware Inner Product Processing.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020
Network Packet Processing Mode-Aware Power Management for Data Center Servers.
IEEE Comput. Archit. Lett., 2020

Co-Adjusting Voltage/Frequency State and Interrupt Rate for Improving Energy-Efficiency of Latency-Critical Applications.
IEEE Access, 2020

Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache.
IEEE Access, 2020

Improving the Efficiency of Power Management via Dynamic Interrupt Management.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
Exploiting OS-Level Memory Offlining for DRAM Power Management.
IEEE Comput. Archit. Lett., 2019

2018
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

VIP: Virtual Performance-State for Efficient Power Management of Virtual Machines.
Proceedings of the ACM Symposium on Cloud Computing, 2018

2017
dist-gem5: Distributed simulation of computer clusters.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

NCAP: Network-Driven, Packet Context-Aware Power Management for Client-Server Architecture.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Janus: supporting heterogeneous power management in virtualized environments.
Proceedings of the 2017 Symposium on Cloud Computing, SoCC 2017, Santa Clara, CA, USA, 2017

2016
Virtual Snooping Coherence for Multi-Core Virtualized Systems.
IEEE Trans. Parallel Distributed Syst., 2016

pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems.
IEEE Comput. Archit. Lett., 2016

2015
vCache: architectural support for transparent and isolated virtual LLCs in virtualized environments.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

2014
vCache: Providing a Transparent View of the LLC in Virtualized Environments.
IEEE Comput. Archit. Lett., 2014

2012
Subspace Snooping: Exploiting Temporal Sharing Stability for Snoop Reduction.
IEEE Trans. Computers, 2012

2010
Virtual Snooping: Filtering Snoops in Virtualized Multi-cores.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Subspace snooping: filtering snoops with operating system support.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010


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