Jaeha Kung
Orcid: 0000-0001-6151-8602
According to our database1,
Jaeha Kung
authored at least 44 papers
between 2011 and 2024.
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Bibliography
2024
One-Spike SNN: Single-Spike Phase Coding with Base Manipulation for ANN-to-SNN Conversion Loss Minimization.
CoRR, 2024
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
NDPipe: Exploiting Near-data Processing for Scalable Inference and Continuous Training in Photo Storage.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
2023
FlexBlock: A Flexible DNN Training Accelerator With Multi-Mode Block Floating Point Support.
IEEE Trans. Computers, September, 2023
Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Improving Hardware Efficiency of a Sparse Training Accelerator by Restructuring a Reduction Network.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A 1V 136.6dB-DR 4kHz-BW $\Delta\Sigma$ Current-to-Digital Converter with a Truncation-Noise-Shaped Baseline-Servo-Loop in 0.18\mu\mathrm{m}$ CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
DBPS: Dynamic Block Size and Precision Scaling for Efficient DNN Training Supported by RISC-V ISA Extensions.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Implication of Optimizing NPU Dataflows on Neural Architecture Search for Mobile Devices.
ACM Trans. Design Autom. Electr. Syst., 2022
AutoRelax: HW-SW Co-Optimization for Efficient SpGEMM Operations With Automated Relaxation in Deep Learning.
IEEE Trans. Emerg. Top. Comput., 2022
A 46-nF/10-MΩ Range 114-aF/0.37-Ω Resolution Parasitic- and Temperature-Insensitive Reconfigurable RC-to-Digital Converter in 0.18-μm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Comput. Archit. Lett., 2022
LightNorm: Area and Energy-Efficient Batch Normalization Hardware for On-Device DNN Training.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
DualPIM: A Dual-Precision and Low-Power CNN Inference Engine Using SRAM- and eDRAM-based Processing-in-Memory Arrays.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
ACM Trans. Design Autom. Electr. Syst., 2021
Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC Operator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Comput. Archit. Lett., 2021
Adaptive Input-to-Neuron Interlink Development in Training of Spike-Based Liquid State Machines.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
ZeBRA: Precisely Destroying Neural Networks with Zero-Data Based Repeated Bit Flip Attack.
Proceedings of the 32nd British Machine Vision Conference 2021, 2021
2020
Balancing Computation Loads and Optimizing Input Vector Loading in LSTM Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Comput. Archit. Lett., 2020
Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache.
IEEE Access, 2020
2019
Noise Tolerance of an Energy-Scalable Deep Learning Model with Two Extreme Bit-Precisions.
Proceedings of the 2019 International SoC Design Conference, 2019
WMixNet: An Energy-Scalable and Computationally Lightweight Deep Learning Accelerator.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Similarity-Based LSTM Architecture for Energy-Efficient Edge-Level Speech Recognition.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Peregrine: A Flexible Hardware Accelerator for LSTM with Limited Synaptic Connection Patterns.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
J. Signal Process. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
PhD thesis, 2017
A Power-Aware Digital Multilayer Perceptron Accelerator with On-Chip Training Based on Approximate Computing.
IEEE Trans. Emerg. Top. Comput., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Dynamic Approximation with Feedback Control for Energy-Efficient Recurrent Neural Network Hardware.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
2015
On the Impact of Energy-Accuracy Tradeoff in a Digital Cellular Neural Network for Image Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
A power-aware digital feedforward neural network platform with backpropagation driven approximate synapses.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
2011
Proceedings of the International SoC Design Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011