Young Hoon Son

According to our database¹, Young Hoon Son authored at least 17 papers between 2012 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2021

GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

2018

Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices.

[BibT_eX]

[DOI]

IEEE Access, 2018

2017

SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

Understanding power-performance relationship of energy-efficient modern DRAM devices.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems.

[BibT_eX]

[DOI]

Hadi Asghari Moghaddam

Young Hoon Son

Jung Ho Ahn

Nam Sung Kim

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015

CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2015

CiDRA: A cache-inspired DRAM resilience architecture.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014

Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2014

Row-buffer decoupling: A case for low-latency DRAM microarchitecture.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013

Scalable high-radix router microarchitecture using a network switch organization.

[BibT_eX]

[DOI]

Jung Ho Ahn

Young Hoon Son

John Kim

ACM Trans. Archit. Code Optim., 2013

Reducing memory access latency with asymmetric DRAM bank organizations.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Young Hoon Son

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