Daniel Chaver

Orcid: 0000-0002-1815-6412

According to our database¹, Daniel Chaver authored at least 32 papers between 2002 and 2021.

Collaborative distances:

Dijkstra number² of three.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2021

RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education.

[BibT_eX]

[DOI]

Sarah L. Harris

Daniel Chaver

Luis Piñuel

José Ignacio Gómez Pérez

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2018

Reuse Detector: Improving the Management of STT-RAM SLLCs.

[BibT_eX]

[DOI]

Roberto Rodríguez-Rodríguez

Comput. J., 2018

2017

Towards completely fair scheduling on asymmetric single-ISA multicore processors.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2017

MIPSfpga: using a commercial MIPS soft-core in computer architecture education.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2017

2016

MIPSfpga: Hands-on learning on a commercial soft-core.

[BibT_eX]

[DOI]

Sarah L. Harris

Robert Owen

Enrique Sedano

Daniel A. Chaver Martinez

Proceedings of the 11th European Workshop on Microelectronics Education, 2016

2015

Write-Aware Replacement Policies for PCM-Based Systems.

[BibT_eX]

[DOI]

Roberto Rodríguez-Rodríguez

Fernando Castro

Daniel Chaver

Rekai González-Alberquilla

Luis Piñuel

Francisco Tirado

Comput. J., 2015

ACFS: a completely fair scheduler for asymmetric single-isa multicore systems.

[BibT_eX]

[DOI]

Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

An OS-Oriented Performance Monitoring Tool for Multicore Systems.

[BibT_eX]

[DOI]

Juan Carlos Saez

Jorge Casas

Abel Serrano

Roberto Rodríguez-Rodríguez

Fernando Castro

Daniel Chaver

Manuel Prieto-Matías

Proceedings of the Euro-Par 2015: Parallel Processing Workshops, 2015

2014

Improving Pelifo Cache Replacement Policy: Hardware Reduction and Thread-Aware Extension.

[BibT_eX]

[DOI]

Rodrígo González-Alberquilla

Francisco Tirado

J. Circuits Syst. Comput., 2014

Online Evaluation Methodology of Laboratory Sessions in Computer Science Degrees.

[BibT_eX]

[DOI]

Inmaculada Pardines

Marcos Sánchez-Élez

Daniel A. Chaver Martinez

José Ignacio Gómez

Rev. Iberoam. de Tecnol. del Aprendiz., 2014

Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

2013

Delivering fairness and priority enforcement on asymmetric multicore systems via OS scheduling.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2013

Reducing writes in phase-change memory environments by using efficient cache replacement policies.

[BibT_eX]

[DOI]

Roberto Rodríguez-Rodríguez

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Reducing Cache Hierarchy Energy Consumption by Predicting Forwarding and Disabling Associative Sets.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2012

OpenIRS-UCM: an open-source multi-platform for interactive response systems.

[BibT_eX]

[DOI]

Carlos García Sánchez

José Antonio López Orozco

Proceedings of the Annual Conference on Innovation and Technology in Computer Science Education, 2012

2011

Hybrid timing-address oriented load-store queue filtering for an x86 architecture.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2011

2010

L1 Data Cache Power Reduction Using a Forwarding Predictor.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

2009

Replacing Associative Load Queues: A Timing-Centric Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2009

Using age registers for a simple load-store queue filtering.

[BibT_eX]

[DOI]

J. Syst. Archit., 2009

2008

Energy reduction of the fetch mechanism through dynamic adaptation.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2008

2006

A Load-Store Queue Design Based on Predictive State Filtering.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Substituting associative load queue with simple hash tables in out-of-order microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005

A Power-Efficient and Scalable Load-Store Queue Design.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Energy-aware fetch mechanism: trace cache and BTB customization.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism..

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2003

Customizing the Branch Predictor to Reduce Complexity and Energy Consumption.

[BibT_eX]

[DOI]

IEEE Micro, 2003

Branch prediction on demand: an energy-efficient solution.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Vectorization of the 2D Wavelet Lifting Transform Using SIMD Extensions.

[BibT_eX]

[DOI]

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002

Wavelet Transform for Large Scale Image Processing on Modern Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing for Computational Science, 2002

Parallel Wavelet Transform for Large Scale Image Processing.

[BibT_eX]

[DOI]

Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2002

Daniel Chaver

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