José Ignacio Gómez

Orcid: 0000-0002-8678-9123

According to our database1, José Ignacio Gómez authored at least 37 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Improving the Representativeness of Simulation Intervals for the Cache Memory System.
IEEE Access, 2024

2023
COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications.
J. Syst. Archit., December, 2023

2022
Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices.
ACM Trans. Embed. Comput. Syst., 2022

Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
Spatio-Temporal Resolution of Irradiance Samples in Machine Learning Approaches for Irradiance Forecasting.
IEEE Access, 2020

2019
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018
A CPU-GPU Parallel Ant Colony Optimization Solver for the Vehicle Routing Problem.
Proceedings of the Applications of Evolutionary Computation, 2018

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015
A power measurement environment for PCIe accelerators.
Comput. Sci. Res. Dev., 2015

System level exploration of a STT-MRAM based level 1 data-cache.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Online Evaluation Methodology of Laboratory Sessions in Computer Science Degrees.
Rev. Iberoam. de Tecnol. del Aprendiz., 2014

Feasibility exploration of NVM based I-cache through MSHR enhancements.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Adaptive Mapping and Parameter Selection Scheme to Improve Automatic Code Generation for GPUs.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

2013
System-level memory management based on statistical variability compensation for frame-based applications.
ACM Trans. Embed. Comput. Syst., 2013

Polyhedral parallel code generation for CUDA.
ACM Trans. Archit. Code Optim., 2013

Design exploration of a NVM based hybrid instruction memory organization for embedded platforms.
Des. Autom. Embed. Syst., 2013

Range query processing on single and multi GPU environments.
Comput. Electr. Eng., 2013

Multi-level Clustering on Metric Spaces Using a Multi-GPU Platform.
Proceedings of the Euro-Par 2013 Parallel Processing, 2013

2012
OpenIRS-UCM: an open-source multi-platform for interactive response systems.
Proceedings of the Annual Conference on Innovation and Technology in Computer Science Education, 2012

Range Query Processing in a Multi-GPU Environment.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

2011
Parallelism on the Nonnegative Matrix Factorization.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

Biclustering and classification analysis in gene expression using Nonnegative Matrix Factorization on multi-GPU systems.
Proceedings of the 11th International Conference on Intelligent Systems Design and Applications, 2011

kNN Query Processing in Metric Spaces Using GPUs.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010
Improving face recognition by combination of natural and Gabor faces.
Pattern Recognit. Lett., 2010

Statistical approach in a system level methodology to deal with process variation.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
System-level process variability compensation on memory organizations: on the scalability of multi-mode memories.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Combining system scenarios and configurable memories to tolerate unpredictability.
ACM Trans. Design Autom. Electr. Syst., 2008

Improving Priority Enforcement via Non-Work-Conserving Scheduling.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

2004
Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications.
IEEE Des. Test Comput., 2004

Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Optimizing the memory bandwidth with loop fusion.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Optimizing the Memory Bandwidth with Loop Morphing.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
Proceedings of the 2003 Design, 2003

SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
Proceedings of the Embedded Software for SoC, 2003

2002
Analysis of simulation-adapted SPEC 2000 benchmarks.
SIGARCH Comput. Archit. News, 2002


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