Freddy Gabbay

Orcid: 0000-0002-6549-7957

According to our database1, Freddy Gabbay authored at least 23 papers between 1997 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
The RISC-V FPGA (RVfpga) Teaching Package.
IEEE Access, 2026

RISC-V and SHA-256 Accelerator Hackathon: A Problem-Based Learning Approach to Hardware-Software Co-Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
An opportunity to improve Data Center Efficiency: Optimizing the Server's Upgrade Cycle.
CoRR, October, 2025

The Effect of Asymmetric Transistor Aging on Systolic Arrays for Mission Critical Machine Learning Applications.
IEEE Access, 2025

Mission Profile-Driven Transistor Aging Modeling and Simulation Flow.
Proceedings of the 33rd IFIP/IEEE International Conference on Very Large Scale Integration, 2025

2024
Teaching Experiences using the RVfpga Package.
CoRR, 2024

Enhancing DNN Computational Efficiency via Decomposition and Approximation.
IEEE Access, 2024

The Impact of Asymmetric Transistor Aging on Clock Tree Design Considerations.
IEEE Access, 2024

Proactive Runtime Detection of Aging-Related Silent Data Corruptions: A Bottom-Up Approach.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture.
IEEE Comput. Archit. Lett., 2023

2022
A Design Flow and Tool for Avoiding Asymmetric Aging.
IEEE Des. Test, 2022

2021
Post-Training Sparsity-Aware Quantization.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

2020
Asymmetric Aging Effect on Modern Microprocessors.
CoRR, 2020

Electromigration-Aware Architecture for Modern Microprocessors.
CoRR, 2020

HCM: Hardware-Aware Complexity Metric for Neural Network Architectures.
CoRR, 2020

2001
The effect of seance communication on multiprocessing systems.
ACM Trans. Comput. Syst., 2001

2000
Early load address resolution via register tracking.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

1999
The "Smart" simulation environment - A tool-set to develop new cache coherency protocols.
J. Syst. Archit., 1999

1998
Using Value Prediction to Increase the Power of Speculative Execution Hardware.
ACM Trans. Comput. Syst., 1998

Improving achievable ILP through value prediction and program profiling.
Microprocess. Microsystems, 1998

The Effect of Instruction Fetch Bandwidth on Value Prediction.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1997
Can Program Profiling Support Value Prediction?
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Smart: An Advanced Shared-Memory Simulator - Towards a System-Level Simulation Environmen.
Proceedings of the MASCOTS 1997, 1997


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