Fernando Castro

Orcid: 0000-0002-2773-3023

According to our database1, Fernando Castro authored at least 29 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Improving the Representativeness of Simulation Intervals for the Cache Memory System.
IEEE Access, 2024

2022
LFOC+: A Fair OS-Level Cache-Clustering Policy for Commodity Multicore Systems.
IEEE Trans. Computers, 2022

Optimization of a line detection algorithm for autonomous vehicles on a RISC-V with accelerator.
J. Comput. Sci. Technol., 2022

2020
Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processors.
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020

2019
LFOC: A Lightweight Fairness-Oriented Cache Clustering Policy for Commodity Multicores.
Proceedings of the 48th International Conference on Parallel Processing, 2019

2018
Reuse Detector: Improving the Management of STT-RAM SLLCs.
Comput. J., 2018

2017
Towards completely fair scheduling on asymmetric single-ISA multicore processors.
J. Parallel Distributed Comput., 2017

CEPRAM: Compression for Endurance in PCM RAM.
J. Circuits Syst. Comput., 2017

PMCTrack: Delivering Performance Monitoring Counter Support to the OS Scheduler.
Comput. J., 2017

2015
Write-Aware Replacement Policies for PCM-Based Systems.
Comput. J., 2015

ACFS: a completely fair scheduler for asymmetric single-isa multicore systems.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

An OS-Oriented Performance Monitoring Tool for Multicore Systems.
Proceedings of the Euro-Par 2015: Parallel Processing Workshops, 2015

2014
Improving Pelifo Cache Replacement Policy: Hardware Reduction and Thread-Aware Extension.
J. Circuits Syst. Comput., 2014

Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

2013
Delivering fairness and priority enforcement on asymmetric multicore systems via OS scheduling.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2013

Reducing writes in phase-change memory environments by using efficient cache replacement policies.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Reducing Cache Hierarchy Energy Consumption by Predicting Forwarding and Disabling Associative Sets.
J. Circuits Syst. Comput., 2012

OpenIRS-UCM: an open-source multi-platform for interactive response systems.
Proceedings of the Annual Conference on Innovation and Technology in Computer Science Education, 2012

2011
Hybrid timing-address oriented load-store queue filtering for an x86 architecture.
IET Comput. Digit. Tech., 2011

2010
Stack filter: Reducing L1 data cache power consumption.
J. Syst. Archit., 2010

L1 Data Cache Power Reduction Using a Forwarding Predictor.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

2009
Replacing Associative Load Queues: A Timing-Centric Approach.
IEEE Trans. Computers, 2009

Using age registers for a simple load-store queue filtering.
J. Syst. Archit., 2009

Stack oriented data cache filtering.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2006
A Load-Store Queue Design Based on Predictive State Filtering.
J. Low Power Electron., 2006

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Substituting associative load queue with simple hash tables in out-of-order microprocessors.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005
A Power-Efficient and Scalable Load-Store Queue Design.
Proceedings of the Integrated Circuit and System Design, 2005

Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism..
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005


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