Carlos Tokunaga

According to our database1, Carlos Tokunaga authored at least 42 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS.
IEEE J. Solid State Circuits, January, 2024

2023
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS.
IEEE J. Solid State Circuits, 2023

A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Analysis of the Effect of Hot Carrier Injection in An Integrated Inductive Voltage Regulator.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

Improving compute in-memory ECC reliability with successive correction.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses.
IEEE Trans. Very Large Scale Integr. Syst., 2021

CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019

2018
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating.
IEEE J. Solid State Circuits, 2017

2016
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging.
IEEE J. Solid State Circuits, 2016

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator.
IEEE J. Solid State Circuits, 2016

Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A fully integrated charge sharing active decap scheme for power supply noise suppression.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS.
IEEE J. Solid State Circuits, 2013

A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.
IEEE J. Solid State Circuits, 2013

Adaptive and Resilient Circuits for Dynamic Variation Tolerance.
IEEE Des. Test, 2013

2012
A 22nm dynamically adaptive clock distribution for voltage droop tolerance.
Proceedings of the Symposium on VLSI Circuits, 2012

Design for test and reliability in ultimate CMOS.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits, 2011

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

2010
Securing Encryption Systems With a Switched Capacitor Current Equalizer.
IEEE J. Solid State Circuits, 2010

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Resilient microprocessor design for high performance & energy efficiency.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Resilient design in scaled CMOS for energy efficiency.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance.
IEEE J. Solid State Circuits, 2009

Secure AES engine with a local switched-capacitor current equalizer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
True Random Number Generator With a Metastability-Based Quality Control.
IEEE J. Solid State Circuits, 2008

Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Low-voltage circuit design for widespread sensing applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Timing yield enhancement through soft edge flip-flop based design.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


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