Davide Ponton

According to our database1, Davide Ponton authored at least 14 papers between 2008 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers.
IEEE Trans. Very Large Scale Integr. Syst., October, 2025

Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications.
Proceedings of the 20th International Conference on PhD Research in Microelectronics and Electronics, 2025

2024
On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

2018
A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm<sup>2</sup> Area w/ 2D Digital-Pre-Distortion and Package Combiner.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

13.2 A digital multimode polar transmitter supporting 40MHz LTE Carrier Aggregation in 28nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Self-aligned open-loop local quadrature phase generator.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique.
Int. J. Circuit Theory Appl., 2015

Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs.
Proceedings of the Nordic Circuits and Systems Conference, 2015

2011
LC-VCO in the 3.3- to 4-GHz Band Implemented in 32-nm Low-Power CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

2010
Design of radio-frequency circuit building blocks in advanced planar and FinFET CMOS technologies.
PhD thesis, 2010

2009
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Assessment of the impact of technology scaling on the performance of LC-VCOs.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008


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