Davood Shahrjerdi
Orcid: 0000-0002-5955-1830Affiliations:
- New York University, Department of Electrical and Computer Engineering, New York, NY, USA
- IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
- University of Texas at Austin, TX, USA (PhD 2008)
- University of Tehran, Iran
According to our database1,
Davood Shahrjerdi
authored at least 16 papers
between 2005 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
Four-Port Probe Stations and SOLR Calibration Standard Design up to 125 GHz on 28 nm CMOS.
CoRR, October, 2025
2020
An Electrochemical Biochip for Measuring Low Concentrations of Analytes With Adjustable Temporal Resolutions.
IEEE Trans. Biomed. Circuits Syst., 2020
2019
IEEE J. Solid State Circuits, 2019
A CMOS Biosensor Array with 1024 3-Electrode Voltammetry Pixels and 93dB Dynamic Range.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Wideband Sliding Correlator-Based Channel Sounder with Synchronization in 65 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Proceedings of the 76th Device Research Conference, 2018
Proceedings of the 76th Device Research Conference, 2018
2017
IEEE Trans. Biomed. Circuits Syst., 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 700 μW 1GS/s 4-bit folding-flash ADC in 65nm CMOS for wideband wireless communications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A 700uW 1GS/s 4-bit Folding-Flash ADC in 65nm CMOS for Wideband Wireless Communications.
CoRR, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2010
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2005
Optimization of the V<sub>T</sub> control method for low-power ultra-thin double-gate SOI logic circuits.
Integr., 2005