Maud Vinet

According to our database1, Maud Vinet authored at least 37 papers between 2009 and 2023.

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Bibliography

2023
Transport characterization of CMOS-based devices fabricated with isotopically-enriched <sup>28</sup>Si for spin qubit applications.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

A Cryogenic Active Router for Qubit Array Biasing from DC to 320 MHz at 100 nm Gate Pitch.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Coupling control in the few-electron regime of quantum dot arrays using 2-metal gate levels in CMOS technology.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

MOS technology for quantum computing: recent progress and perspectives for scaling up.
Proceedings of the Device Research Conference, 2021

2020
19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Thin-Film FD-SOI BIMOS Topologies for ESD Protection.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Si MOS technology for spin-based quantum computing.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

Towards a scalable quantum computer.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018


2017
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K.
Microelectron. Reliab., 2017

Design considerations for optimization of pull-in stability margin in electrostatic N/MEM relays.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

SOI CMOS technology for quantum information processing.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices.
Proceedings of the 47th European Solid-State Device Research Conference, 2017


2016


Analog performance of strained SOI nanowires down to 10K.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Delay partitioning helps reducing variability in 3DVLSI.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Towards high density 3D interconnections.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Piezoresistive transduction optimization of p-doped poly-Silicon NEMS.
Proceedings of the 45th European Solid State Device Research Conference, 2015

A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Variability of planar Ultra-Thin Body and Buried oxide (UTBB) FDSOI MOSFETs.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
The Coupled Atom Transistor: A first realization with shallow donors implanted in a FDSOI silicon nanowire.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Variability in Fully Depleted MOSFETs.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012


2011
Mass Production of Silicon MOS-SETs: Can We Live with Nano-Devices' Variability?
Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011


2009
System on Wafer: A New Silicon Concept in SiP.
Proc. IEEE, 2009


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