Deepak M. Mathew

Orcid: 0000-0001-5855-0169

According to our database1, Deepak M. Mathew authored at least 17 papers between 2015 and 2021.

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Bibliography

2021
Advanced heterogeneous memory subsystems for energy-constrained computing = Fortgeschrittene heterogene Speichersubsysteme für Computersysteme mit limitiertem Energieverbrauch.
PhD thesis, 2021

Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling.
IEEE Access, 2021

2020
An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

2019
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

2018
Efficient coding scheme for DDR4 memory subsystems.
Proceedings of the International Symposium on Memory Systems, 2018

The Role of Memories in Transprecision Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An analysis on retention error behavior and power consumption of recent DDR4 DRAMs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improving the error behavior of DRAM by exploiting its Z-channel property.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A Platform to Analyze DDR3 DRAM's Power and Retention Time.
IEEE Des. Test, 2017

A Bank-Wise DRAM Power Model for System Simulations.
Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017

Using run-time reverse-engineering to optimize DRAM refresh.
Proceedings of the International Symposium on Memory Systems, 2017

2016
A new bank sensitive DRAMPower model for efficient design space exploration.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

ConGen: An Application Specific DRAM Memory Controller Generator.
Proceedings of the Second International Symposium on Memory Systems, 2016

Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Efficient reliability management in SoCs - an approximate DRAM perspective.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs.
Proceedings of the 2015 International Symposium on Memory Systems, 2015


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