Bastien Giraud
According to our database1,
Bastien Giraud
authored at least 46 papers
between 2007 and 2023.
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Bibliography
2023
Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro.
Proceedings of the IEEE International Memory Workshop, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution.
ACM J. Emerg. Technol. Comput. Syst., 2022
An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper.
Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022
Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2021
A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs.
Proceedings of the 47th ESSCIRC 2021, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications.
CoRR, 2020
Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
2018
Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Proceedings of the International Symposium on Rapid System Prototyping, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
DRC<sup>2</sup>: Dynamically Reconfigurable Computing Circuit based on memory architecture.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
2015
IEEE J. Solid State Circuits, 2015
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
2010
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
2007
A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007