Diandian Zhang

According to our database, Diandian Zhang authored at least 14 papers between 2007 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A High-Sensitivity Wake-up Receiver Using Tunnel Diode for ISM Band.

Bingru Wu, Diandian Zhang, Tao Ma, Ruixuan Jiang, Hanming Gao, Guanghui Liu

Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

2021

OCR with the Deep CNN Model for Ligature Script-Based Languages like Manchu.

Diandian Zhang, Yan Liu, Zhuowei Wang, Depei Wang

Sci. Program., 2021

2014

Improving ESL power models using switching activity information from timed functional models.

Stefan Schürmans, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Xiaotao Chen

Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

2013

Efficient Implementation of Application-Aware Spinlock Control in MPSoCs.

Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout

Int. J. Embed. Real Time Commun. Syst., 2013

Creation of ESL power models for communication architectures using automatic calibration.

Stefan Schürmans, Diandian Zhang, Dominik Auras, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, Lun Wang

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Application-aware spinlock control using a hardware scheduler in MPSoC platforms.

Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout

Proceedings of the 2012 International Symposium on System on Chip, 2012

2011

Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis.

Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, Rainer Leupers

Int. J. Embed. Real Time Commun. Syst., 2011

2010

Optimized communication architecture of MPSoCs with a hardware scheduler: A system view.

Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

2009

Integrated verification approach during ADL-driven processor design.

Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr

Microelectron. J., 2009

Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves.

David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr

IACR Cryptol. ePrint Arch., 2009

Task management in MPSoCs: An ASIP approach.

Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves.

David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rudolf Mathar

Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

2008

Power-efficient Instruction Encoding Optimization for Various Architecture Classes.

Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr

J. Comput., 2008

2007

Power-efficient Instruction Encoding Optimization for Embedded Processors.

Anupam Chattopadhyay, Diandian Zhang, David Kammler, Ernst Martin Witte

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007