Ernst Martin Witte

According to our database1, Ernst Martin Witte authored at least 19 papers between 2005 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2012
An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

A 2.78 mm<sup>2</sup> 65 nm CMOS gigabit MIMO iterative detection and decoding receiver.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Automatic Generation of Memory Interfaces for ASIPs.
Int. J. Embed. Real Time Commun. Syst., 2010

2009
A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding
CoRR, 2009

Efficient And Portable SDR Waveform Development: The Nucleus Concept
CoRR, 2009

Complexity-Efficient Enumeration Techniques for Soft-Input, Soft-Output Sphere Decoding
CoRR, 2009

Combining orthogonalized partial metrics: Efficient enumeration for soft-input sphere decoder.
Proceedings of the IEEE 20th International Symposium on Personal, 2009

Automatic generation of memory interfaces.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Searching in the Delta Lattice: An Efficient MIMO Detection for Iterative Receivers.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

2008
Power-efficient Instruction Encoding Optimization for Various Architecture Classes.
J. Comput., 2008

2007
Application-Specific Instruction-Set Processor for Retinex-Like Image and Video Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Power-efficient Instruction Encoding Optimization for Embedded Processors.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Design of Application Specific Instruction-Set Processor for image and video filtering.
Proceedings of the 14th European Signal Processing Conference, 2006

ASIP design and synthesis for non linear filtering in image processing.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Automatic ADL-based operand isolation for embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Optimization Techniques for ADL-Driven RTL Processor Synthesis.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005


  Loading...