Dinesh Pamunuwa

According to our database, Dinesh Pamunuwa authored at least 38 papers between 2000 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays.

Tian Qin, Simon J. Bleiker, Sunil Rana, Frank Niklaus, Dinesh Pamunuwa

IEEE Access, 2018

2015

Zero-load predictive model for performance analysis in deflection routing NoCs.

Awet Yemane Weldezion, Matt Grange, Axel Jantsch, Hannu Tenhunen, Dinesh Pamunuwa

Microprocess. Microsystems, 2015

Design Methodologies, Models and Tools for Very-Large-Scale Integration of NEM Relay-Based Circuits.

Tian Qin, Sunil Rana, Dinesh Pamunuwa

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Energy and Latency Optimization in NEM Relay-Based Digital Circuits.

Sunil Rana, Tian Qin, Antonios Bazigos, Daniel Grogg, Michel Despont, Christopher Lawrence Ayala, Christoph Hagleitner, Adrian Mihai Ionescu, Roberto Canegallo, Dinesh Pamunuwa

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

Modelling NEM relays for digital circuit applications.

Sunil Rana, Tian Qin, Dinesh Pamunuwa, Daniel Grogg, Michel Despont, Yu Pu, Christoph Hagleitner

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns.

Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Axel Jantsch, Hannu Tenhunen

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2011

The Promises and Limitations of 3-D Integration.

Axel Jantsch, Matthew Grange, Dinesh Pamunuwa

Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

3-D integration and the limits of silicon computation.

Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks.

Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion

Proceedings of the NOCS 2011, 2011

Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning.

Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits.

Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints.

Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Scalability of network-on-chip communication architecture for 3-D meshes.

Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Designing Reliable Digital Molecular Electronic Circuits.

Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert

Proceedings of the Nano-Net - 4th International ICST Conference, 2009

Design of Robust Molecular Electronic Circuits.

Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits.

Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng

Proceedings of the IEEE International Conference on 3D System Integration, 2009

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.

Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008

Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime.

Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

IEEE Trans. Very Large Scale Integr. Syst., 2008

Application of Molecular Electronics Devices in Digital Circuit Design.

Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert

Proceedings of the Nano-Net - Third International ICST Conference, 2008

Memory Technology for Extended Large-Scale Integration in Future Electronics Applications.

Dinesh Pamunuwa

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Delay-Balanced Smart Repeaters for On-Chip Global Signaling.

Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Early selection of system implementation choice among SoC, SoP and 3-D Integration.

Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen

Proceedings of the 2007 IEEE International SOC Conference, 2007

Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs.

Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime.

Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

2005

Modeling delay and noise in arbitrarily coupled RC trees.

Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses.

Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen

Proceedings of the Integrated Circuit and System Design, 2005

2004

A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.

Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen

Integr., 2004

Crosstalk immune interconnect driver design.

Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen

Proceedings of the 2004 International Symposium on System-on-Chip, 2004

2003

Maximizing throughput over parallel wire structures in the deep submicrometer regime.

Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

IEEE Trans. Very Large Scale Integr. Syst., 2003

Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures.

Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch

Proceedings of the IFIP VLSI-SoC 2003, 2003

Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees.

Dinesh Pamunuwa, Shauki Elassaad

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A global wire planning scheme for Network-on-Chip.

Jian Liu, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Analytic Modeling of Interconnects for Deep Sub-Micron Circuits.

Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects.

Dinesh Pamunuwa, Hannu Tenhunen

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

On dynamic delay and repeater insertion.

Hannu Tenhunen, Dinesh Pamunuwa

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Optimising bandwidth over deep sub-micron interconnect.

Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Repeater Insertion To Minimise Delay In Coupled Interconnects.

Dinesh Pamunuwa, Hannu Tenhunen

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000

Combating digital noise in high speed ULSI circuits using binary BCH encoding.

Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000