Ananda Samajdar

According to our database1, Ananda Samajdar authored at least 16 papers between 2017 and 2023.

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Bibliography

2023
AIrchitect: Automating Hardware Architecture and Mapping Optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
AIRCHITECT: Learning Custom Architecture Design and Mapping Space.
CoRR, 2021

Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration.
CoRR, 2021

Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Data Orchestration in Deep Learning Accelerators
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01767-4, 2020

A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

CLAN: Continuous Learning using Asynchronous Neuroevolution on Commodity Edge Devices.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018
A Communication-Centric Approach for Designing Flexible DNN Accelerators.
IEEE Micro, 2018

SCALE-Sim: Systolic CNN Accelerator.
CoRR, 2018

GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Rethinking NoCs for Spatial Neural Network Accelerators.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017


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