Dong-Jin Chang
Orcid: 0000-0002-4763-1219
According to our database1,
Dong-Jin Chang
authored at least 18 papers
between 2016 and 2025.
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Bibliography
2025
Retrieval Augmented Large Language Model System for Comprehensive Drug Contraindications.
CoRR, August, 2025
2022
J. Comput. Des. Eng., 2022
A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
An innovative strategy for standardized, structured, and interoperable results in ophthalmic examinations.
BMC Medical Informatics Decis. Mak., 2021
A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration.
IEEE J. Solid State Circuits, 2021
Comput. Methods Programs Biomed., 2021
IEEE Access, 2021
Sequential Lung Nodule Synthesis Using Attribute-Guided Generative Adversarial Networks.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2021 - 24th International Conference, Strasbourg, France, September 27, 2021
An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst., 2020
2019
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration.
IEEE J. Solid State Circuits, 2019
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC.
IEEE J. Solid State Circuits, 2016