Dongsheng Liu
Orcid: 0000-0001-5571-1932Affiliations:
- Huazhong University of Science and Technology, School of Integrated Circuits, Jinyinhu Laboratory, Wuhan, China (PhD 2007)
According to our database1,
Dongsheng Liu authored at least 73 papers
between 2008 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
A Phase Switching Fractional Output Divider With Split-DTC-Based Nonlinear Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2026
A 240 × 180 Event-Based Vision Sensor ROIC With Global Threshold Voltage Calibration Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026
CoRR, January, 2026
Microelectron. J., 2026
2025
A 1-8 b Reconfigurable 64 Mb STT-MRAM Near-Memory Computing Macro for Energy-Efficient AI-Edge Devices.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2025
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025
2024
An 8×8 Event-Based Vision Infrared Sensor ROIC With Adaptive Threshold Voltage Generation Circuit.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
IEEE Trans. Circuits Syst. II Express Briefs, September, 2024
A Low-Phase-Noise Wide-Tuning-Range Mode-Switching Oscillator Using Multi-Magnetic-Coupling and Active-Source-Degenerating Techniques.
IEEE J. Solid State Circuits, September, 2024
A Dark Count Rate Self-Adjusting Charge Pump With Negative Feedback Control for SPAD Array Biasing.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2024
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
Microelectron. J., 2024
A 206.4 dBc/Hz FoMT Class-F23 VCO using nonlinear-capacitance-transforming technique.
Microelectron. J., 2024
A Fractional-N DTC-based ADPLL using path-select multi-delay line TDC and true fractional division technique.
Microelectron. J., 2024
An Efficient and Configurable Hardware Architecture of Polynomial Modular Operation for CRYSTALS-Kyber and Dilithium.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
Proceedings of the 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A 40nm 1.26µ/Op Energy-Efficient CRYSTALS-KYBER Post-Quantum Crypto-Processor with Comprehensive Side Channel Security Analysis and Countermeasures.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS.
Microelectron. J., November, 2023
A 12-bit single slope ADC with multi-step structure and ramp calibration technique for image sensors.
Microelectron. J., September, 2023
Fractional Spurs Reduction Technique Using Probability Density Shaping Sigma-Delta Modulator and Fractional Frequency Divider.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
A Fractional-<i>N C</i>P-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS.
Microelectron. J., February, 2023
A Flexible and High-Performance Lattice-Based Post-Quantum Crypto Secure Coprocessor.
IEEE Trans. Ind. Informatics, 2023
A DTC-based Fractional-<i>N</i> DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications.
Microelectron. J., 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Flexible and Efficient Implementation of CRYSTALS-KYBER SIMD RISC-V Coprocessor Based on Customized Vector Instruction-Set Extension.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 40nm $\boldsymbol{2.76}\boldsymbol{\mu}\mathbf{J}/\mathbf{Op}$ Energy-Efficient Secure Post-Quantum Crypto-Processor for Crystals-Kyber on Module-LWE.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A DC Offset Cancellation Circuit Using Digital Assistance Technique and Self-Calibrating Comparator for RF Transceiver.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
An Efficient Unstructured Sparse Convolutional Neural Network Accelerator for Wearable ECG Classification Device.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 640×512 ROIC with optimized BDI input stage and low power output buffer for CQDs-based infrared image sensor.
Microelectron. J., 2022
Microelectron. J., 2022
Efficient hardware design of a deep U-net model for pixel-level ECG classification in healthcare device.
Microelectron. J., 2022
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022
A High Throughput and Configurable Pseudo-random Number Extension Generator for Lattice-based Post-quantum Cryptography.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
Efficient Hardware Architecture of Convolutional Neural Network for ECG Classification in Wearable Healthcare Device.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer.
Microelectron. J., 2021
An accurate ISF-based analysis and simulation method for phase noise in LC/Ring oscillators.
Microelectron. J., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Efficient Hardware Architecture for Epileptic Seizure Detection using EEG Signals based on 1D-CNN.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Flexible and Generic Gaussian Sampler With Power Side-Channel Countermeasures for Quantum-Secure Internet of Things.
IEEE Internet Things J., 2020
2019
A Resource-Efficient and Side-Channel Secure Hardware Implementation of Ring-LWE Cryptographic Processor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 0.03- to 3.6-GHz Frequency Synthesizer With Self-Biased VCO and Quadrature-Input Quadrature-Output Frequency Divider.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Analysis and optimization of seamless switching golden states of multi-modulus divider in software defined ∑-Δ Frequency synthesizer.
Microelectron. J., 2019
A Fully Integrated HF RFID Tag Chip With LFSR-based Light-weight Tripling Mutual Authentication Protocol.
IEEE Access, 2019
A 0.045- to 2.5- GHz Frequency Synthesizer with TDC-based AFC and Phase Switching Multi-Modulus Divider.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
A Configurable Architecture of ANN in Hardware with Resource-Efficient Reusable Neuron.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
A 35µW Receiver Front-End with 35% wireless energy harvesting efficiency for Wearable Medical Applications.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A Quadrature Single Side-Band Mixer with Passive Negative Resistance in Software-Defined Frequency Synthesizer.
Sensors, 2018
2017
An Efficient and Flexible Hardware Implementation of the Dual-Field Elliptic Curve Cryptographic Processor.
IEEE Trans. Ind. Electron., 2017
J. Circuits Syst. Comput., 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
A Low-Cost Low-Power Ring Oscillator-Based Truly Random Number Generator for Encryption on Smart Cards.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Implementation of a resource-constrained ECC processor with power analysis countermeasure.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Design and Implementation of An ECC-Based Digital Baseband Controller for RFID Tag Chip.
IEEE Trans. Ind. Electron., 2015
A High Sensitivity Analog Front-end Circuit for Semi-Passive HF RFID Tag Applied to Implantable Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 2.45-GHz W-level output power CMOS power amplifier with adaptive bias and integrated diode linearizer.
Microelectron. J., 2015
2014
Design and Implementation of a RF Powering Circuit for RFID Tags or Other Batteryless Embedded Devices.
Sensors, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2011
Sensors, 2011
IEEE Commun. Lett., 2011
2010
Microelectron. J., 2010
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2010
2008
Clock control strategy of four-phase Dickson charge pump for power efficiency improvement.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008