Takashi Nakada

IEICE Trans. Inf. Syst., 2022

2021

Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing.

[BibT_eX]

[DOI]

Integr., 2021

Flexible Bayesian Inference by Weight Transfer for Robust Deep Neural Networks.

[BibT_eX]

[DOI]

Thi Thu Thao Khong

IEICE Trans. Inf. Syst., 2021

2020

Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2020

An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2020

Bayes without Bayesian Learning for Resisting Adversarial Attacks.

[BibT_eX]

[DOI]

Thi Thu Thao Khong

Proceedings of the Eighth International Symposium on Computing and Networking, 2020

2019

Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation.

[BibT_eX]

[DOI]

Renyuan Zhang

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

GPGPU Implementation of Variational Bayesian Gaussian Mixture Models.

[BibT_eX]

[DOI]

Hiroki Nishimoto

Proceedings of the 2019 Seventh International Symposium on Computing and Networking, 2019

2018

Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing.

[BibT_eX]

[DOI]

IEEE Micro, 2018

A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing.

[BibT_eX]

[DOI]

Shinya Takamaeda-Yamazaki

IEICE Trans. Inf. Syst., 2018

A programmable analog calculation unit for vector computations.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

Efficient Multitasking on FPGA Using HDL-Based Checkpointing.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017

An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation.

[BibT_eX]

[DOI]

Tomoki Hatanaka

Hiroshi Ueki

Toru Shimizu

IEICE Trans. Inf. Syst., 2017

Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing.

[BibT_eX]

[DOI]

Renyuan Zhang

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Compression and Aggregation for Optimizing Information Transmission in Distributed CNN.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing.

[BibT_eX]

[DOI]

Shinya Takamaeda-Yamazaki

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2016

An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis.

[BibT_eX]

[DOI]

Toru Shimizu

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Normally-off power management for sensor nodes of global navigation satellite system.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

2015

Runtime multi-optimizations for energy efficient on-chip interconnections1.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Data Science and Data Intensive Systems, 2015

2014

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Data-aware power management for periodic real-time systems with non-volatile memory.

[BibT_eX]

[DOI]

Toru Shimizu

Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Normally-off computing project: Challenges and opportunities.

[BibT_eX]

[DOI]

Shinobu Miwa

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Performance modeling for designing NoC-based multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2011

An Instruction Mapping Scheme for FU Array Accelerator.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

LAPP: A Low Power Array Accelerator with Binary Compatibility.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

An efficient and reliable 1.5-way processor by fusion of space and time redundancies.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011

2010

A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

An Instruction Decomposition Method for Reconfigurable Decoders.

[BibT_eX]

[DOI]

Kazuhiro Yoshimura

Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, 2010

2008

A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions.

[BibT_eX]

[DOI]

Masahiro Konishi

IPSJ Trans. Syst. LSI Des. Methodol., 2008

A Functional Unit with Small Variety of Highly Reliable Cells.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008

2007

An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 40th Annual Simulation Symposium (ANSS-40 2007), 2007

2006

An accurate and efficient simulation-based analysis for worst case interruption delay.

[BibT_eX]

[DOI]

Masahiro Konishi

Proceedings of the 2006 International Conference on Compilers, 2006

Design and Implementation of aWorkload Specific Simulator.

[BibT_eX]

[DOI]

Tomoaki Tsumura

Proceedings of the Proceedings 39th Annual Simulation Symposium (ANSS-39 2006), 2006

2004

Design and Implementation of a High Speed Microprocessor Simulator BurstScalar.

[BibT_eX]

[DOI]