Keiko Abe

According to our database, Keiko Abe authored at least 15 papers between 2005 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Novel memory hierarchy with e-STT-MRAM for near-future applications.

Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.

Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.

Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Novel nonvolatile memory hierarchies to realize "normally-off mobile processors".

Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Pictogram-based tablet application enabling patient input of emotions and behaviors.

Teruyoshi Hishiki, Hiroki Yasui, Yoshiko Matsunaga, Megumi Itoshima, Keiko Abe, Takahiko Norose, Takuro Tamura

Proceedings of the AMIA 2014, 2014

2013

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.

Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation.

Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2010

Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies.

Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).

Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009

Perspectives and Issues in 3D-IC from Designers' Point of View.

Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture.

Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2006

Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices.

Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

3D on-chip networking technology based on post-silicon devices for future networks-on-chip.

Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

2005

Physical random number generators for cryptographic application in mobile devices.

Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita

Proceedings of the 31st European Solid-State Circuits Conference, 2005