Elio Guidetti

According to our database1, Elio Guidetti authored at least 10 papers between 2007 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2025
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture.
CoRR, May, 2025

2024
Design-Space Exploration of Integrated Frequency Synthesis Architecture for Wake-Up Radio in Low-Power Wi-Fi Applications.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2024

2022
An Integrated Low-power 802.11ba Wake-up Radio for IoT with Embedded Microprocessor.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2017
14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
The Orlando Project: A 28 nm FD-SOI Low Memory Embedded Neural Network ASIC.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2016

2013
A 14-bit extended-range incremental ΣΔ ADC matlab-model based on 90nm CMOS-technology.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2011
A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2007
An Ultra-Low Power Data Aggregation System for Wireless Micro Sensor Networks.
J. Low Power Electron., 2007

A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing.
J. Low Power Electron., 2007

Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology.
J. Comput. Sci. Technol., 2007


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