Anastasios Psarras

Orcid: 0000-0001-6151-9242

According to our database1, Anastasios Psarras authored at least 18 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024

2022
Virtual-Channel Flow Control Across Mesochronous Clock Domains.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

2020
The Mesochronous Dual-Clock FIFO Buffer.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2018
Low-power dual-edge-triggered synchronous latency-insensitive systems.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

2017
Networks-on-Chip With Double-Data-Rate Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Dual-Clock Multiple-Queue Shared Buffer.
IEEE Trans. Computers, 2017

Active Thermoelectric Cooling Solutions for Airspace Applications: the THERMICOOL Project.
IEEE Access, 2017

2016
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing.
IEEE Trans. Computers, 2016

RapidLink: A network-on-chip architecture with double-data-rate links.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

CrossOver: Clock domain crossing under virtual-channel flow control.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Timing-resilient Network-on-Chip architectures.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

ElastiStore: An elastic buffer architecture for Network-on-Chip routers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hardware primitives for the synthesis of multithreaded elastic systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


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