Francesco Bruschi

Orcid: 0000-0001-5669-2788

According to our database1, Francesco Bruschi authored at least 44 papers between 2000 and 2024.

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Bibliography

2024
Cognitive Oracles: Provable on-chain assessment through Validity Machine Learning.
Proceedings of the IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2024

Decentralized Updates of IoT and Edge Devices.
Proceedings of the Advanced Information Networking and Applications, 2024

2023
A Decentralized Approach to Award Game Achievements.
Proceedings of the IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2023

2022
A new approach for Bitcoin pool-hopping detection.
Comput. Networks, 2022

A Protocol for On-Chain Tenders.
Proceedings of the 2022 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2022

2021
Tunneling Trust Into the Blockchain: A Merkle Based Proof System for Structured Documents.
IEEE Access, 2021

A privacy preserving identification protocol for smart contracts.
Proceedings of the IEEE Symposium on Computers and Communications, 2021

2020
Acknowledging Value of Personal Information: a Privacy Aware Data Market for Health and Social Research.
Proceedings of the 3rd Distributed Ledger Technology Workshop Co-located with ITASEC 2020, 2020

A Decentralized System for Fair Token Distribution and Seamless Users Onboarding.
Proceedings of the IEEE Symposium on Computers and Communications, 2020

2018
Mine with it or sell it: the superhashing power dilemma.
SIGMETRICS Perform. Evaluation Rev., 2018

2017
User context estimation for public travel assistance and intelligent service scheduling.
Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems, 2017

Time of arrival cumulative probability in public transportation travel assistance.
Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems, 2017

2016
Efficient Hardware Design of Iterative Stencil Loops.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Reconstruction of public transport state.
Proceedings of the 19th IEEE International Conference on Intelligent Transportation Systems, 2016

2014
On How to Efficiently Implement Regular Expression Matching on FPGA-Based Systems.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013
An Algorithm for Extended Dynamic Range Video in Embedded Systems.
Proceedings of the SENSORNETS 2013, 2013

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
On-chip network resource management design and validation.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

An efficient Quantum-Dot Cellular Automata adder.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Designing and validating access policies to reconfigurable resources in Multiprocessor Systems on chip.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
A Transform-Parametric Approach to Boolean Matching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008
Static Analysis of Transaction-Level Communication Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Design of Communication Infrastructures for Reconfigurable Systems.
Proceedings of the Languages for Embedded Systems and their Applications, 2008

A Requirements-Driven Simulation Framework for Communication Infrastructures Design.
Proceedings of the Forum on specification and Design Languages, 2008

An architecture for dynamically reconfigurable real time audio processing systems.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

2007
An efficient cost-based canonical form for Boolean matching.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A Unified Approach to Canonical Form-based Boolean Matching.
Proceedings of the 44th Design Automation Conference, 2007

2006
A SystemC-based Framework of Communication Architecture.
Proceedings of the Forum on specification and Design Languages, 2006

Synthesis of Object Oriented Models on Reconfigurable Hardware.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

2005
A Framework for the Functional Verification of SystemC Models.
Int. J. Parallel Program., 2005

Mapping Interface Method Calls over OCP Buses.
Proceedings of the Forum on specification and Design Languages, 2005

Aspect Orientation in System Level Design.
Proceedings of the Forum on specification and Design Languages, 2005

A Data Oriented Approach to the Design of Reconfigurable Stream Decoders.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

2004
Methodological issues in the system level design of embedded systems.
PhD thesis, 2004

Virtual Community in the Classroom: An Innovating Tool for Elearning.
Proceedings of the EDUTECH, 2004

Synthesis of Dynamic Class Loading Specifications on Reconfigurable Hardware.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

A Design Methodology for the Exploitation of High Level Communication Synthesis.
Proceedings of the 2004 Design, 2004

2003
Synthesis of Complex Control Structures from Behavioral SystemC Models.
Proceedings of the 2003 Design, 2003

SystemC-VHDL Co-Simulation and Synthesis in the HW Domain.
Proceedings of the 2003 Design, 2003

Static analysis of transaction-level models.
Proceedings of the 40th Design Automation Conference, 2003

2002
Error Simulation Based on the SystemC Design Description Language.
Proceedings of the 2002 Design, 2002

2000
An approach to functional testing of VLIW architectures.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000


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