Vincenzo Rana
Orcid: 0000-0001-6851-1737
According to our database1,
Vincenzo Rana
authored at least 60 papers
between 2006 and 2022.
Collaborative distances:
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Bibliography
2022
Proceedings of the 2022 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2022
2021
Tunneling Trust Into the Blockchain: A Merkle Based Proof System for Structured Documents.
IEEE Access, 2021
Proceedings of the IEEE Symposium on Computers and Communications, 2021
2020
Acknowledging Value of Personal Information: a Privacy Aware Data Market for Health and Social Research.
Proceedings of the 3rd Distributed Ledger Technology Workshop Co-located with ITASEC 2020, 2020
Proceedings of the IEEE Symposium on Computers and Communications, 2020
2018
ACM Trans. Cyber Phys. Syst., 2018
SIGMETRICS Perform. Evaluation Rev., 2018
2017
User context estimation for public travel assistance and intelligent service scheduling.
Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems, 2017
Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems, 2017
Proceedings of the 2017 IEEE EMBS International Conference on Biomedical & Health Informatics, 2017
2016
Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices.
ACM Trans. Embed. Comput. Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016
Proceedings of the 19th IEEE International Conference on Intelligent Transportation Systems, 2016
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016
2014
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms.
ACM Trans. Reconfigurable Technol. Syst., 2014
A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces.
Proceedings of the IEEE World Forum on Internet of Things, 2014
BlueSentinel: a first approach using iBeacon for an energy efficient occupancy detection system.
Proceedings of the 1st ACM Conference on Embedded Systems for Energy-Efficient Buildings, 2014
An Open-Source, Efficient, and Parameterizable Hardware Implementation of the AES Algorithm.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
2013
Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms.
IEEE Des. Test, 2013
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the 13th Latin American Test Workshop, 2012
Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
B<sup>2</sup>IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor Networks.
Proceedings of the 2012 Ninth International Conference on Wearable and Implantable Body Sensor Networks, 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Operating system runtime management of partially dynamically reconfigurable embedded systems.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010
2009
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the FPL 2008, 2008
Proceedings of the Languages for Embedded Systems and their Applications, 2008
Proceedings of the Forum on specification and Design Languages, 2008
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
The Shining embedded system design methodology based on self dynamic reconfigurable architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
A novel SoC design methodology combining adaptive software and reconfigurable hardware.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006