Antonio Miele
Orcid: 0000-0003-3197-0723Affiliations:
- Politecnico di Milano, Milano, Italy
According to our database1,
Antonio Miele
authored at least 98 papers
between 2004 and 2024.
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Bibliography
2024
CoRR, 2024
2023
IEEE Trans. Computers, October, 2023
IEEE Trans. Computers, April, 2023
Adaptive Workload Distribution for Accuracy-aware DNN Inference on Collaborative Edge Platforms.
CoRR, 2023
Resilience of Deep Learning applications: a systematic survey of analysis and hardening techniques.
CoRR, 2023
Poster Abstract: Energy vs. Quality of Approximate Non-volatile Writes in Intermittent Computing.
Proceedings of the 21st ACM Conference on Embedded Networked Sensor Systems, 2023
Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
A Runtime Resource Management and Provisioning Middleware for Fog Computing Infrastructures.
ACM Trans. Internet Things, 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Computers, 2022
IEEE Embed. Syst. Lett., 2022
Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor Systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
2021
Energy-Efficient Mobile Robot Control via Run-time Monitoring of Environmental Complexity and Computing Workload.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Guest Editor's Introduction: Special Section on Reliability-Aware Design and Analysis Methods for Digital Systems: From Gate to System Level.
IEEE Trans. Emerg. Top. Comput., 2020
CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Computers, 2020
A methodology for the design and deployment of distributed cyber-physical systems for smart environments.
Future Gener. Comput. Syst., 2020
Asynchronous Corner Tracking Algorithm Based on Lifetime of Events for DAVIS Cameras.
Proceedings of the Advances in Visual Computing - 15th International Symposium, 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the 25th International Conference on Pattern Recognition, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Scalable analytical model for reliability measures in aging VLSI by interacting Markovian agents.
Perform. Evaluation, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
A Runtime Resource Management Policy for OpenCL Workloads on Heterogeneous Multicores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
SIGBED Rev., 2018
Exploring Heterogeneous Task-Level Parallelism in a BMA Video Coding Application using System-Level Simulation.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Approximation-aware coordinated power/performance management for heterogeneous multi-cores.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Performance/Reliability-Aware Resource Management for Many-Cores in Dark Silicon Era.
IEEE Trans. Computers, 2017
Scalable analytical model of the reliability of multi-core systems-on-chip by interacting Markovian agents.
Proceedings of the 11th EAI International Conference on Performance Evaluation Methodologies and Tools, 2017
Epistemic uncertainty propagation in a Weibull environment for a two-core system-on-chip.
Proceedings of the 2nd International Conference on System Reliability and Safety, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
2016
IEEE Trans. Computers, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
A lifetime-aware runtime mapping approach for many-core systems in the dark silicon era.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Quality of Service Driven Runtime Resource Allocation in Reconfigurable HPC Architectures.
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016
2015
An orchestrated approach to efficiently manage resources in heterogeneous system architectures.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
A System-Level Simulation Framework for Evaluating Resource Management Policies for Heterogeneous System Architectures.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
2014
A fault-injection methodology for the system-level dependability analysis of multiprocessor embedded systems.
Microprocess. Microsystems, 2014
Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
Proceedings of the IEEE 30th International Conference on Data Engineering, Chicago, 2014
A lightweight and open-source framework for the lifetime estimation of multicore systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
IEEE Trans. Computers, 2013
A data-mining approach to preference-based data ranking founded on contextual information.
Inf. Syst., 2013
A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs.
Int. J. Embed. Real Time Commun. Syst., 2013
J. Electron. Test., 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs.
Proceedings of the 2012 International Symposium on System on Chip, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs.
IEEE Trans. Computers, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Combined architecture and hardening techniques exploration for reliable embedded system design.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
A multi-objective genetic algorithm framework for design space exploration of reliable FPGA-based systems.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the EDBT 2009, 2009
A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
J. Electron. Test., 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
Proceedings of the 5th International Workshop on Software Engineering and Middleware, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
PoLiDBMS: Design and Prototype Implementation of a DBMS for Portable Devices.
Proceedings of the Twelfth Italian Symposium on Advanced Database Systems, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004