Daniel Chillet
Orcid: 0000-0003-3414-9084
According to our database1,
Daniel Chillet
authored at least 66 papers
between 1996 and 2023.
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Bibliography
2023
IEEE Des. Test, December, 2023
2022
ACM Trans. Design Autom. Electr. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
2021
A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Energy-Efficient Scheduling of Real-Time Tasks in Reconfigurable Homogeneous Multicore Platforms.
IEEE Trans. Syst. Man Cybern. Syst., 2020
Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip Architecture.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
2019
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019
2018
Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects.
ACM J. Emerg. Technol. Comput. Syst., 2018
Proceedings of the 13th International Conference on Evaluation of Novel Approaches to Software Engineering, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
J. Low Power Electron., 2016
Proceedings of the 28th IEEE International Conference on Tools with Artificial Intelligence, 2016
2015
Proceedings of the Intelligent Software Methodologies, Tools and Techniques, 2015
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015
2014
Microprocess. Microsystems, 2014
Special issue on design and architectures of real-time image processing in embedded systems.
J. Real Time Image Process., 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Intrinsic Fault Tolerance of Hopfield Artificial Neural Network Model for Task Scheduling Technique in SoC.
Proceedings of the NCTA 2014 - Proceedings of the International Conference on Neural Computation Theory and Applications, part of IJCCI 2014, Rome, Italy, 22, 2014
Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014
2013
IEEE Trans. Ind. Informatics, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
Communication cost reduction for hardware tasks placed on homogeneous reconfigurable resource.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
2012
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Open-people: An open platform for estimation and optimizations of energy consumption.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
2011
SIGARCH Comput. Archit. News, 2011
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network.
J. Syst. Archit., 2011
Int. J. Reconfigurable Comput., 2011
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Parallel Evaluation of Hopfield Neural Networks.
Proceedings of the NCTA 2011, 2011
2010
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures.
Int. J. Reconfigurable Comput., 2010
Mesh and Fat-Tree comparison for dynamically reconfigurable applications.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
2009
Int. J. Reconfigurable Comput., 2009
High-Level Exploration for Dynamic Reconfiguration Management.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
2008
Structure mémoire reconfigurable. Vers une structure de stockage faible consommation.
Tech. Sci. Informatiques, 2008
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
2007
Proceedings of the International Joint Conference on Neural Networks, 2007
Proceedings of the 15th European Signal Processing Conference, 2007
2006
EURASIP J. Adv. Signal Process., 2006
2005
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Co-Design of Massively Parallel Embedded Processor Architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
2003
Tech. Sci. Informatiques, 2003
2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture.
Proceedings of the IEEE International Conference on Acoustics, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the International Conference on Compilers, 2002
2001
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.
Proceedings of the SOC Design Methodologies, 2001
2000
J. VLSI Signal Process., 2000
Teaching hardware/software system codesign using CAD tools: a case study in image synthesis.
IEEE Trans. Educ., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1998
Proceedings of the 9th European Signal Processing Conference, 1998
1997
VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
1996
Proceedings of the 8th European Signal Processing Conference, 1996