Sujoy Sinha Roy

Orcid: 0000-0002-9805-5389

According to our database1, Sujoy Sinha Roy authored at least 80 papers between 2011 and 2024.

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Bibliography

2024
High-Speed Design of Post Quantum Cryptography With Optimized Hashing and Multiplication.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

ModHE: Modular Homomorphic Encryption Using Module Lattices Potentials and Limitations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Exploring the Advantages and Challenges of Fermat NTT in FHE Acceleration.
IACR Cryptol. ePrint Arch., 2024

SASTA: Ambushing Hybrid Homomorphic Encryption Schemes with a Single Fault.
IACR Cryptol. ePrint Arch., 2024

REPQC: Reverse Engineering and Backdooring Hardware Accelerators for Post-quantum Cryptography.
CoRR, 2024

2023
High-speed SABER key encapsulation mechanism in 65nm CMOS.
J. Cryptogr. Eng., November, 2023

A Unified Cryptoprocessor for Lattice-Based Signature and Key-Exchange.
IEEE Trans. Computers, June, 2023

KaLi: A Crystal for Post-Quantum Security Using Kyber and Dilithium.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Medha: Microcoded Hardware Accelerator for computing on Encrypted Data.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Kavach: Lightweight masking techniques for polynomial arithmetic in lattice-based cryptography.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2023

Towards a constant-time implementation of isogeny-based signature, SQISign.
IACR Cryptol. ePrint Arch., 2023

Parallel Hardware for Isogeny-based VDF: Attacker's Perspective.
IACR Cryptol. ePrint Arch., 2023

Towards High-speed ASIC Implementations of Post-Quantum Cryptography.
IACR Cryptol. ePrint Arch., 2023

A Hardware Implementation of MAYO Signature Scheme.
IACR Cryptol. ePrint Arch., 2023

PROTEUS: A Tool to generate pipelined Number Theoretic Transform Architectures for FHE and ZKP applications.
IACR Cryptol. ePrint Arch., 2023

REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2023

Secure and Efficient Post-Quantum Cryptography in Hardware and Software (Dagstuhl Seminar 23152).
Dagstuhl Reports, 2023

2022
On Exploiting Message Leakage in (Few) NIST PQC Candidates for Practical Message Recovery Attacks.
IEEE Trans. Inf. Forensics Secur., 2022

Will You Cross the Threshold for Me? Generic Side-Channel Assisted Chosen-Ciphertext Attacks on NTRU-based KEMs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Time-Memory Trade-Offs for Saber+ on Memory-Constrained RISC-V Platform.
IEEE Trans. Computers, 2022

Magnifying Side-Channel Leakage of Lattice-Based Cryptosystems With Chosen Ciphertexts: The Case Study of Kyber.
IEEE Trans. Computers, 2022

Backdooring Post-Quantum Cryptography: Kleptographic Attacks on Lattice-based KEMs.
IACR Cryptol. ePrint Arch., 2022

Exploring RNS for Isogeny-based Cryptography.
IACR Cryptol. ePrint Arch., 2022

KaLi: A Crystal for Post-Quantum Security.
IACR Cryptol. ePrint Arch., 2022

2021
Time-memory Trade-offs for Saber+ on Memory-constrained RISC-V.
IACR Cryptol. ePrint Arch., 2021

Accelerator for Computing on Encrypted Data.
IACR Cryptol. ePrint Arch., 2021

Generic Side-Channel Assisted Chosen-Ciphertext Attacks on Streamlined NTRU Prime.
IACR Cryptol. ePrint Arch., 2021

Design Space Exploration of SABER in 65nm ASIC.
IACR Cryptol. ePrint Arch., 2021

2020
High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Generic Side-channel attacks on CCA-secure lattice-based PKE and KEMs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

HEAWS: An Accelerator for Homomorphic Encryption on the Amazon AWS FPGA.
IEEE Trans. Computers, 2020

Magnifying Side-Channel Leakage of Lattice-Based Cryptosystems with Chosen Ciphertexts: The Case Study of Kyber.
IACR Cryptol. ePrint Arch., 2020

On Exploiting Message Leakage in (few) NIST PQC Candidates for Practical Message Recovery and Key Recovery Attacks.
IACR Cryptol. ePrint Arch., 2020

Drop by Drop you break the rock - Exploiting generic vulnerabilities in Lattice-based PKE/KEMs using EM-based Physical Attacks.
IACR Cryptol. ePrint Arch., 2020

Compact domain-specific co-processor for accelerating module lattice-based key encapsulation mechanism.
IACR Cryptol. ePrint Arch., 2020

Optimized Polynomial Multiplier Architectures for Post-Quantum KEM Saber.
IACR Cryptol. ePrint Arch., 2020

Compact domain-specific co-processor for accelerating module lattice-based KEM.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Constant-time BCH Error-Correcting Code.
IACR Cryptol. ePrint Arch., 2019

FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data.
IACR Cryptol. ePrint Arch., 2019

SaberX4: High-throughput Software Implementationof Saber Key Encapsulation Mechanism.
IACR Cryptol. ePrint Arch., 2019

Generic Side-channel attacks on CCA-secure lattice-based PKE and KEM schemes.
IACR Cryptol. ePrint Arch., 2019

Pushing the speed limit of constant-time discrete Gaussian sampling. A case study on Falcon.
IACR Cryptol. ePrint Arch., 2019

SaberX4: High-Throughput Software Implementation of Saber Key Encapsulation Mechanism.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Pushing the speed limit of constant-time discrete Gaussian sampling. A case study on the Falcon signature scheme.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Saber on ARM CCA-secure module lattice-based key encapsulation on ARM.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

HEPCloud: An FPGA-Based Multicore Processor for FV Somewhat Homomorphic Function Evaluation.
IEEE Trans. Computers, 2018

Constant-Time Discrete Gaussian Sampling.
IEEE Trans. Computers, 2018

Arithmetic of $$\tau $$ τ -adic expansions for lightweight Koblitz curve cryptography.
J. Cryptogr. Eng., 2018

Saber: Module-LWR based key exchange, CPA-secure encryption and CCA-secure KEM.
IACR Cryptol. ePrint Arch., 2018

Teaching HW/SW codesign with a Zynq ARM/FPGA SoC.
Proceedings of the 12th European Workshop on Microelectronics Education, 2018

2017
Public Key Cryptography on Hardware Platforms: Design and Analysis of Elliptic Curve and Lattice-based Cryptoprocessors ; Public key cryptografie op hardware platforms: ontwerp en analyse van elliptische krommen en rooster-gebaseerde crypto-processors.
PhD thesis, 2017

High-Performance Ideal Lattice-Based Cryptography on 8-Bit AVR Microcontrollers.
ACM Trans. Embed. Comput. Syst., 2017

Hardware Assisted Fully Homomorphic Function Evaluation and Encrypted Search.
IEEE Trans. Computers, 2017

2016
Masking ring-LWE.
J. Cryptogr. Eng., 2016

Efficient Finite field multiplication for isogeny based post quantum cryptography.
IACR Cryptol. ePrint Arch., 2016

Embedded Security.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A Tiny Coprocessor for Elliptic Curve Cryptography over the 256-bit NIST Prime Field.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Ring-LWE: Applications to Cryptography and Their Efficient Realization.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Additively Homomorphic Ring-LWE Masking.
Proceedings of the Post-Quantum Cryptography - 7th International Workshop, 2016

2015
Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Modular Hardware Architecture for Somewhat Homomorphic Function Evaluation.
IACR Cryptol. ePrint Arch., 2015

Lightweight Coprocessor for Koblitz Curves: 283-bit ECC Including Scalar Conversion with only 4300 Gates.
IACR Cryptol. ePrint Arch., 2015

A masked ring-LWE implementation.
IACR Cryptol. ePrint Arch., 2015

Efficient Ring-LWE Encryption on 8-bit AVR Processors.
IACR Cryptol. ePrint Arch., 2015

24.1 Circuit challenges from cryptography.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Compact and Side Channel Secure Discrete Gaussian Sampling.
IACR Cryptol. ePrint Arch., 2014

Efficient Software Implementation of Ring-LWE Encryption.
IACR Cryptol. ePrint Arch., 2014

High-speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems.
IACR Cryptol. ePrint Arch., 2014

Compact Ring-LWE Cryptoprocessor.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014

2013
Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Compact Hardware Implementation of Ring-LWE Cryptosystems.
IACR Cryptol. ePrint Arch., 2013

High Precision Discrete Gaussian Sampling on FPGAs.
Proceedings of the Selected Areas in Cryptography - SAC 2013, 2013

2012
Generalized high speed Itoh-Tsujii multiplicative inversion architecture for FPGAs.
Integr., 2012

A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA Platforms.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

2011
Revisiting the Itoh-Tsujii Inversion Algorithm for FPGA Platforms.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Scalar Multiplication on Koblitz Curves using tau<sup>2</sup>-NAF.
IACR Cryptol. ePrint Arch., 2011

Accelerating Itoh-Tsujii multiplicative inversion algorithm for FPGAs.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2011


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