Gaurav Narang

According to our database, Gaurav Narang authored at least 6 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads.

Harsh Sharma, Gaurav Narang, Janardhan Rao Doppa, Ümit Y. Ogras, Partha Pratim Pande

CoRR, 2024

2023

Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework.

Gaurav Narang, Aryan Deshwal, Raid Ayoub, Michael Kishinevsky, Janardhan Rao Doppa, Partha Pratim Pande

ACM Trans. Design Autom. Electr. Syst., September, 2023

Uncertainty-Aware Online Learning for Dynamic Power Management in Large Manycore Systems.

Gaurav Narang, Raid Ayoub, Michael Kishinevsky, Janardhan Rao Doppa, Partha Pratim Pande

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

2016

Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework.

Prakhar Raj Gupta, G. S. Visweswaran, Gaurav Narang, Anuj Grover

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015

Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance.

Gaurav Narang, Pragya Sharma, Mansi Jain, Anuj Grover

Proceedings of the 28th International Conference on VLSI Design, 2015

Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems.

Gaurav Narang, Alexander Fell, Prakhar Raj Gupta, Anuj Grover

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015