Christian Pilato

Orcid: 0000-0001-9315-1788

Affiliations:
  • Politecnico di Milano, Italy


According to our database1, Christian Pilato authored at least 104 papers between 2007 and 2024.

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Bibliography

2024
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach.
CoRR, 2024

Foundation Models in Augmentative and Alternative Communication: Opportunities and Challenges.
CoRR, 2024

2023
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023

Generating Posit-Based Accelerators With High-Level Synthesis.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics.
ACM Trans. Reconfigurable Technol. Syst., June, 2023

Optimizing the Use of Behavioral Locking for High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

A Survey of FPGA Optimization Methods for Data Center Energy Efficiency.
IEEE Trans. Sustain. Comput., 2023

CPS Workshop 2023 Proceedings.
CoRR, 2023

Platform-Aware FPGA System Architecture Generation based on MLIR.
CoRR, 2023

Towards High-Level Synthesis of Quantum Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications.
ACM Trans. Design Autom. Electr. Syst., 2022

HOLL: Program Synthesis for Higher OrderLogic Locking.
CoRR, 2022

HOLL: Program Synthesis for Higher Order Logic Locking.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2022

Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Composable Design Space Exploration Framework to Optimize Behavioral Locking.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

ALICE: an automatic design flow for eFPGA redaction.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Designing ML-resilient locking at register-transfer level.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

High-level design methods for hardware security: is it the right choice? invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Protecting Hardware IP Cores During High-Level Synthesis.
Behavioral Synthesis for Hardware Security, 2022

2021
ASSURE: RTL Locking Against an Untrusted Foundry.
IEEE Trans. Very Large Scale Integr. Syst., 2021

CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching.
ACM Trans. Embed. Comput. Syst., 2021

Automatic Generation of Heterogeneous SoC Architectures With Secure Communications.
IEEE Embed. Syst. Lett., 2021

A Survey on Domain-Specific Memory Architectures.
CoRR, 2021

On the Optimization of Behavioral Logic Locking for High-Level Synthesis.
CoRR, 2021

Compiler Infrastructure for Specializing Domain-Specific Memory Templates.
CoRR, 2021

High-Level Synthesis of Security Properties via Software-Level Abstractions.
CoRR, 2021

Exploring eFPGA-based Redaction for IP Protection.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics.
Proceedings of the IEEE International Conference on Cluster Computing, 2021

2020
Agile SoC Development with Open ESP.
CoRR, 2020

Agile SoC Development with Open ESP : Invited Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Is Register Transfer Level Locking Secure?
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Black-Hat High-Level Synthesis: Myth or Reality?
IEEE Trans. Very Large Scale Integr. Syst., 2019

CAD-Base: An Attack Vector into the Electronics Supply Chain.
ACM Trans. Design Autom. Electr. Syst., 2019

TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

High-Level Synthesis of Benevolent Trojans.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
The Case for Polymorphic Registers in Dataflow Computing.
Int. J. Parallel Program., 2018

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis.
IEEE Embed. Syst. Lett., 2018

Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis.
IEEE Des. Test, 2018

TAO: techniques for algorithm-level obfuscation during high-level synthesis.
Proceedings of the 55th Annual Design Automation Conference, 2018

DarkMem: Fine-grained power management of local memories for accelerators in embedded systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Bridging the Gap Between Software and Hardware Designers Using High-Level Synthesis.
Proceedings of the Parallel Computing is Everywhere, 2017

2016
Editorial: Special Issue on Innovative Design Methods for Smart Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2016

A Survey and Evaluation of FPGA High-Level Synthesis Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Performance Estimation of Task Graphs Based on Path Profiling.
Int. J. Parallel Program., 2016

Scala-Based Domain-Specific Language for Creating Accelerator-Based SoCs.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems.
Proceedings of the 53rd Annual Design Automation Conference, 2016

On the design of scalable and reusable accelerators for big data applications.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip.
Proceedings of the 2016 International Conference on Compilers, 2016

2015
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocess. Microsystems, 2015

2014
A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces.
Proceedings of the IEEE World Forum on Internet of Things, 2014

Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

System-level memory optimization for high-level synthesis of component-based SoCs.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Effective Reconfigurable Design: The FASTER Approach.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs.
Int. J. Embed. Real Time Commun. Syst., 2013

Dataflow computing with Polymorphic Registers.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

A framework for effective exploitation of partial reconfiguration in dataflow computing.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

The FASTER vision for designing dynamically reconfigurable systems.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

Bambu: A modular framework for the high level synthesis of memory-intensive applications.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A2B: An integrated framework for designing heterogeneous and reconfigurable systems.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Ant Colony Optimization for mapping, scheduling and placing in reconfigurable systems.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Runtime adaptation on dataflow HPC platforms.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
TaBit: A framework for task graph to bitstream generation.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Smart technologies for effective reconfiguration: The FASTER approach.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Automatic run-time manager generation for reconfigurable MPSoC architectures.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs.
Proceedings of the 2012 International Symposium on System on Chip, 2012

On the automatic integration of hardware accelerators into FPGA-based embedded systems.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

An open-source design and validation platform for reconfigurable systems.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

On the Development of a Runtime Reconfigurable Multicore System-on-Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011
A design methodology for the automatic sizing of standard-cell libraries.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Combined architecture and hardening techniques exploration for reliable embedded system design.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A design methodology to implement memory accesses in high-level synthesis.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Evaluating Static CMOS Complex Cells in Technology Mapping.
Proceedings of the ARCS 2011, 2011

SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels.
Proceedings of the ARCS 2011, 2011

A runtime adaptive controller for supporting hardware components with variable latency.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Design methodologies for improving embedded systems with hardware accelerators.
PhD thesis, 2010

Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.
IEEE Micro, 2010

A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Performance estimation for task graphs combining sequential path profiling and control dependence regions.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Performance modeling of parallel applications on MPSoCs.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems.
Proceedings of the Genetic and Evolutionary Computation Conference, 2009

HW/SW methodologies for synchronization in FPGA multiprocessors.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Improving evolutionary exploration to area-time optimization of FPGA designs.
J. Syst. Archit., 2008

Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis.
Proceedings of the IEEE Congress on Evolutionary Computation, 2008

2007
An Evolutionary Approach to Area-Time Optimization of FPGA designs.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Fitness inheritance in evolutionary and multi-objective high-level synthesis.
Proceedings of the IEEE Congress on Evolutionary Computation, 2007


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