Ghaith Tarawneh
Orcid: 0000-0001-6415-1658
  According to our database1,
  Ghaith Tarawneh
  authored at least 19 papers
  between 2012 and 2022.
  
  
Collaborative distances:
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Bibliography
  2022
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture.
    
  
    IET Comput. Digit. Tech., 2022
    
  
  2018
    IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
    
  
    Proceedings of the Companion of the 2018 ACM Conference on Computer Supported Cooperative Work and Social Computing, 2018
    
  
Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools.
    
  
    Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018
    
  
  2017
Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression.
    
  
    Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
    
  
    Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
    
  
    Proceedings of the Parallel Computing is Everywhere, 2017
    
  
    Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017
    
  
    Proceedings of the 2017 Forum on Specification and Design Languages, 2017
    
  
Energy-efficient approximate multiplier design using bit significance-driven logic compression.
    
  
    Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
    
  
    Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017
    
  
    Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017
    
  
  2016
Formal verification of clock domain crossing using gate-level models of metastable flip-flops.
    
  
    Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
    
  
  2014
    IEEE Trans. Very Large Scale Integr. Syst., 2014
    
  
Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip.
    
  
    Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
    
  
    Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
    
  
  2012
    Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
    
  
    Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
    
  
    Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012