Giorgio Baccarani

Orcid: 0000-0001-7365-5495

Affiliations:
  • University of Bologna, Italy


According to our database1, Giorgio Baccarani authored at least 37 papers between 1987 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Awards

IEEE Fellow

IEEE Fellow 1999, "For contributions to the scaled silicon device theory.".

Timeline

Legend:

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Links

Online presence:

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Bibliography

2018
TCAD study of DLC coatings for large-area high-power diodes.
Microelectron. Reliab., 2018

Electrical characterization of epoxy-based molding compounds for next generation HV ICs in presence of moisture.
Microelectron. Reliab., 2018

2015
Theoretical analyses and modeling for nanoelectronics.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2014
A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs.
Proceedings of the 44th European Solid State Device Research Conference, 2014

TCAD analysis of HCS degradation in LDMOS devices under AC stress conditions.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Impact of crystallographic orientation and impurity scattering in Graphene-Base Heterojunction Transistors for Terahertz Operation.
Proceedings of the 44th European Solid State Device Research Conference, 2014

TCAD modeling of encapsulation layer in high-voltage, high-temperature operation regime.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Deterministic solution of the 1D Boltzmann transport equation: Application to the study of current transport in nanowire FETs.
Microelectron. J., 2013

Modeling and characterization of hot-carrier stress degradation in power MOSFETs (invited).
Proceedings of the European Solid-State Device Research Conference, 2013

Gate stack optimization to minimize power consumption in super-lattice fets.
Proceedings of the European Solid-State Device Research Conference, 2013

DC and small-signal numerical simulation of graphene base transistor for terahertz operation.
Proceedings of the European Solid-State Device Research Conference, 2013

Boosting InAs TFET on-current above 1 mA/μm with no leakage penalty.
Proceedings of the European Solid-State Device Research Conference, 2013

Complementary n- and p-type TFETs on the same InAs/Al0.05Ga0.95Sb platform.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Drain-conductance optimization in nanowire TFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2003
A Single-Scan Algorithm for Connected Components Labelling in a Traffic Monitoring Application.
Proceedings of the Image Analysis, 13th Scandinavian Conference, 2003

2000
An Analytical, Temperature-dependent Model for Majority- and Minority-carrier Mobility in Silicon Devices.
VLSI Design, 2000

1998
Recent Advances in Device Simulation Using Standard Transport Models.
VLSI Design, 1998

Analog synthesis of nonlinear functions based on fuzzy logic.
IEEE J. Solid State Circuits, 1998

1996
Highly constrained neural networks for industrial quality control.
IEEE Trans. Neural Networks, 1996

A photodiode cell for applications to position and motion estimation sensors.
IEEE Trans. Ind. Electron., 1996

Automatic synthesis of analog fuzzy controllers: a hardware and software approach.
IEEE Trans. Ind. Electron., 1996

A silicon compiler of analog fuzzy controllers: from behavioral specifications to layout.
IEEE Trans. Fuzzy Syst., 1996

An ASIC chip set for parallel fuzzy database mining.
IEEE Micro, 1996

Device simulation for smart integrated systems (DESSIS).
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995
On the Structure and Closure-Condition of the Hydrodynamic Model.
VLSI Design, 1995

An enhanced two-level Boolean synthesis methodology for fuzzy rules minimization.
IEEE Trans. Fuzzy Syst., 1995

A 2D-DCT low-power architecture for H.261 coders.
Proceedings of the 1995 International Conference on Acoustics, 1995

1994
Hydrodynamic simulation of semiconductor devices operating at low temperature.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993
Modeling impact ionization in a BJT by means of spherical harmonics expansion of the Boltzmann transport equation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

An array-processor based architecture for classification problems.
Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992
Numerical modeling of advanced semiconductor devices.
IBM J. Res. Dev., 1992

A novel metric for nearest-neighbor classification of hand-written digits.
Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992

1991
Efficient 3-D simulation of complex structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1990
Three-dimensional simulation of VLSI structures.
Eur. Trans. Telecommun., 1990

1989
Adaptive mesh generation preserving the quality of the initial grid.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988
A new discretization strategy of the semiconductor equations comprising momentum and energy balance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1987
Sensitivity Analysis for Device Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987


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