Giuseppe Zaza

According to our database1, Giuseppe Zaza authored at least 9 papers between 1991 and 1995.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

1995
Design-Flow and Synthesis for ASICs: A Case Study.
Proceedings of the 32st Conference on Design Automation, 1995

1994
ALADIN: a multilevel testability analyzer for VLSI system design.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Quantitative Evaluation of Formal Based Synthesis in ASIC Design.
Proceedings of the Theorem Provers in Circuit Design, 1994

1993
A design methodology for the correct specification of VLSI systems.
Microprocess. Microprogramming, 1993

An Expert Solution to Functional Testability Analysis of VLSI Circuits.
Proceedings of the SEKE'93, 1993

Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
Specification and Formal Synthesis of Digital Circuits.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1992

A multi level testability assistant for VLSI design.
Proceedings of the conference on European design automation, 1992

1991
The Patricia testability analysis tool.
Microprocessing and Microprogramming, 1991


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