Gorker Alp Malazgirt

Orcid: 0000-0002-2331-9212

According to our database1, Gorker Alp Malazgirt authored at least 15 papers between 2012 and 2019.

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Bibliography

2019
Advanced analytics through FPGA based query processing and deep reinforcement learning.
PhD thesis, 2019

TauRieL: Targeting Traveling Salesman Problem with a deep reinforcement learning inspired architecture.
CoRR, 2019

2017
AxleDB: A novel programmable query processing platform on FPGA.
Microprocess. Microsystems, 2017

Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures.
J. Syst. Archit., 2017

2016
Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory.
Comput. Sci. Eng., 2016

Taxim: A Toolchain for Automated and Configurable Simulation for Embedded Multiprocessor Design.
CoRR, 2016

Big Data and HPC Acceleration with Vivado HLS.
Proceedings of the FPGAs for Software Programmers, 2016

2015
Customizing VLIW processors from dynamically profiled execution traces.
Microprocess. Microsystems, 2015

High Level Synthesis Based Hardware Accelerator Design for Processing SQL Queries.
Proceedings of the 12th FPGAworld Conference 2015, 2015

Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Exploring Embedded Symmetric Multiprocessing with Various On-Chip Architectures.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

2014
MIPT: Rapid exploration and evaluation for migrating sequential algorithms to multiprocessing systems with multi-port memories.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

Application specific multi-port memory customization in FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2012
High-Level verifiable data-path Synthesis for DSP systems.
Proceedings of the 20th Signal Processing and Communications Applications Conference, 2012

A Verifiable High Level Data Path Synthesis Framework.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012


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