Nehir Sönmez

Orcid: 0000-0002-3125-6450

According to our database1, Nehir Sönmez authored at least 24 papers between 2006 and 2023.

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Bibliography

2023
Functional Verification of a RISC-V Vector Accelerator.
IEEE Des. Test, June, 2023


2022

2020

2019
Evaluation of a Rack-Scale Disaggregated Memory Prototype for Cloud Data Centers.
Proceedings of the 30th International Workshop on Rapid System Prototyping, 2019

2017
AxleDB: A novel programmable query processing platform on FPGA.
Microprocess. Microsystems, 2017

2016
Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory.
Comput. Sci. Eng., 2016

Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique.
Proceedings of the High Performance Computing - Third Latin American Conference, 2016

Big Data and HPC Acceleration with Vivado HLS.
Proceedings of the FPGAs for Software Programmers, 2016

Bluespec SystemVerilog.
Proceedings of the FPGAs for Software Programmers, 2016

2015
High Level Synthesis Based Hardware Accelerator Design for Processing SQL Queries.
Proceedings of the 12th FPGAworld Conference 2015, 2015

Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
PAMS: Pattern Aware Memory System for embedded systems.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2012
A multicore emulator with a profiling Infrastructure for transactional memory on FPGA.
PhD thesis, 2012

Resource-bounded multicore emulation using Beefarm.
Microprocess. Microsystems, 2012

A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2009
Taking the heat off transactions: Dynamic selection of pessimistic concurrency control.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2008
The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment.
Proceedings of the 5th Conference on Computing Frontiers, 2008

2007
unreadTVar: Extending Haskell Software Transactional Memory for Performance.
Proceedings of the Eighth Symposium on Trends in Functional Programming, 2007

2006
SIxD: A Configurable Application-Specific SISD/SIMD Microprocessor Soft-Core.
Proceedings of the International Symposium on System-on-Chip, 2006


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