Nikolaos Kavvadias

According to our database1, Nikolaos Kavvadias authored at least 26 papers between 2001 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Toolflow for Parallelization of Embedded Software in Multicore DSP Platforms.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Design space exploration tools for the ByoRISC configurable processor family.
CoRR, 2014

Generating and evaluating application-specific hardware extensions.
CoRR, 2014

Compiling Scilab to high performance embedded multicore systems.
Microprocess. Microsystems, 2013

Hardware design space exploration using HercuLeS HLS.
Proceedings of the 17th Panhellenic Conference on Informatics, 2013

The HercuLeS high-level synthesis environment.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

From Scilab to multicore embedded systems: Algorithms and methodologies.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Design of fixed-point rounding operators for the VHDL-2008 standard.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

Efficient Hardware Looping Units for FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Scalable register bypassing for FPGA-based processors.
Microprocess. Microsystems, 2009

Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.
IEEE Trans. Computers, 2008

Development of a customized processor architecture for accelerating genetic algorithms.
Microprocessors and Microsystems, 2007

A portable specification of zero-overhead looping control hardware applied to embedded processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Instruction level energy modeling for pipelined processors.
J. Embedded Computing, 2005

Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications.
Proceedings of the 2005 Design, 2005

Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Measurements analysis of the software-related power consumption in microprocessors.
IEEE Trans. Instrumentation and Measurement, 2004

The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms.
Proceedings of the Integrated Circuit and System Design, 2004

Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors.
Proceedings of the Integrated Circuit and System Design, 2004

Tradeoffs in the Design Space Exploration of Application-Specific Processors.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Instrumentation Set-up for Instruction Level Power Modeling.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Memory hierarchy exploration for low power architectures in embedded multimedia applications.
Proceedings of the 2001 International Conference on Image Processing, 2001