Guan-Yi Lin

According to our database, Guan-Yi Lin authored at least 4 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices.

Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, De-Qi You, Fang-Yi Chen, Andrew Lee, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations.

Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsih Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Win-San Khwa, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2009

A multi-format Blu-ray player SoC in 90nm CMOS.

Chi-Cheng Ju, Tsu-Ming Liu, Chih-Chieh Yang, Shih-Hung Lin, Kuo-Pin Lan, Chien-Hua Wu, Ting-Hsun Wei, Chi-Chin Lien, Jiun-Yuan Wu, Chih-Hao Hsiao, Te-Wei Chen, Yeh-Lin Chu, Guan-Yi Lin, Yung-Chang Chang, Kung-Sheng Lin, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Chien-Hung Lin, Yung-Teng Lin, Shang-Ming Lee, Ya-Ching Yang, Yu-Lun Cheng, Chen-Chia Lee, Ming-Shiang Lai, Wen-Hua Wu, Ted Hu, Chao-Wei Tseng, Chen-Yu Hsiao, Wei-Liang Lee, Bo-Jiun Chen, Pao-Cheng Chiu, Shang-Ping Chen, Kun-Hsien Li, Kuan-Hua Chao, Chien-Ming Chen, Chuan-Cheng Hsiao, Jeffrey Ju, Wei-Hung Huang, Chi-Hui Wang, Hung-Sung Li, Evan Su, Joe Chen

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2005

A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining.

Shih-Hao Wang, Wen-Hsiao Peng, Yuwen He, Guan-Yi Lin, Cheng-Yi Lin, Shih-Chien Chang, Chung-Neng Wang, Tihao Chiang

J. VLSI Signal Process., 2005