Chuan-Jia Jhang

According to our database¹, Chuan-Jia Jhang authored at least 7 papers between 2021 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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2024

A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme.

[BibT_eX]

[DOI]

Tsung-Yung Jonathan Chang

Meng-Fan Chang

IEEE J. Solid State Circuits, January, 2024

2023

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, March, 2023

Challenges in Circuits of Nonvolatile Compute-In-Memory for Edge AI Chips.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W.

[BibT_eX]

[DOI]

Tsung-Yung Jonathan Chang

Meng-Fan Chang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices.

[BibT_eX]

[DOI]

Tsung-Yung Jonathan Chang

Meng-Fan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Chuan-Jia Jhang

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