Jui-Jen Wu
According to our database1,
Jui-Jen Wu
authored at least 12 papers
between 2009 and 2024.
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Bibliography
2024
34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2015
Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations.
IEEE J. Solid State Circuits, 2015
An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros.
IEEE J. Solid State Circuits, 2015
2014
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme.
IEEE J. Solid State Circuits, 2014
19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V<sub>TH</sub> Read-Port, and Offset Cell VDD Biasing Techniques.
IEEE J. Solid State Circuits, 2013
2012
A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
A Large Sigma V <sub>TH</sub> /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.
IEEE J. Solid State Circuits, 2011
2010
A Differential Data-Aware Power-Supplied (D <sup>2</sup> AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications.
IEEE J. Solid State Circuits, 2010
2009
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs.
IEEE J. Solid State Circuits, 2009