Gyunam Jeon
According to our database1,
Gyunam Jeon
authored at least 9 papers
between 2016 and 2024.
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Bibliography
2024
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2019
10 GHz Standing Wave Oscillator Based Clock Distribution Network Considering Distributed Capacitance.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation.
Proceedings of the 2019 International SoC Design Conference, 2019
2018
Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme.
Integr., 2018
Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
2017
A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1<sup>st</sup> speculative tap.
Proceedings of the International SoC Design Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016