Han Xu
Orcid: 0000-0002-2469-1286Affiliations:
- Tsinghua University, Beijing, China
 
  According to our database1,
  Han Xu
  authored at least 12 papers
  between 2018 and 2023.
  
  
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
- 
    on orcid.org
 
On csauthors.net:
Bibliography
  2023
  2022
Senputing: An Ultra-Low-Power Always-On Vision Perception Chip Featuring the Deep Fusion of Sensing and Computing.
    
  
    IEEE Trans. Circuits Syst. I Regul. Pap., 2022
    
  
In-situ self-powered intelligent vision system with inference-adaptive energy scheduling for BNN-based always-on perception.
    
  
    Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
    
  
A 2.17μW@120fps Ultra-Low-Power Dual-Mode CMOS Image Sensor with Senputing Architecture.
    
  
    Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
    
  
  2021
MACSen: A Processing-In-Sensor Architecture Integrating MAC Operations Into Image Sensor for Ultra-Low-Power BNN-Based Intelligent Visual Perception.
    
  
    IEEE Trans. Circuits Syst. II Express Briefs, 2021
    
  
NS-MD: Near-Sensor Motion Detection With Energy Harvesting Image Sensor for Always-On Visual Perception.
    
  
    IEEE Trans. Circuits Syst. II Express Briefs, 2021
    
  
Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing.
    
  
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
    
  
A 5.9μW Ultra-Low-Power Dual-Resolution CIS Chip of Sensing-with-Computing for Always-on Intelligent Visual Devices.
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
    
  
A 4.57 μW@120fps Vision System of Sensing with Computing for BNN-Based Perception Applications.
    
  
    Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
    
  
  2020
CDS-RSRAM: a Reconfigurable SRAM Architecture to Reduce Read Power with Column Data Segmentation.
    
  
    Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
    
  
Utilizing Direct Photocurrent Computation and 2D Kernel Scheduling to Improve In-Sensor-Processing Efficiency.
    
  
    Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
    
  
  2018
Energy-Efficient SRAM Design with Data-Aware Dual-Modes L0T Storage Cell for CNN Processors.
    
  
    Proceedings of the 31st IEEE International System-on-Chip Conference, 2018