Harmander Singh

According to our database1, Harmander Singh authored at least 13 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Power and performance aware memory-controller voting mechanism.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2010
Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2007
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Power Gating with Multiple Sleep Modes.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A dual-V<sub>DD</sub> boosted pulsed bus technique for low power and low leakage operation.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Fine grained multi-threshold CMOS for enhanced leakage reduction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Bus encoding for total power reduction using a leakage-aware buffer configuration.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization.
Proceedings of the 2004 Design, 2004

Leakage-and crosstalk-aware bus encoding for total power reduction.
Proceedings of the 41th Design Automation Conference, 2004


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